Current counting analog-to-digital converter for load current sensing including dynamically biased comparator

• US 9,484,944 B2
• Filed: 07/11/2014
• Issued: 11/01/2016
• Est. Priority Date: 07/11/2014
• Status: Expired due to Fees

• Current Assignee: Qualcomm, Inc.
• Original Assignee: Qualcomm, Inc.
• Inventors: Peluso, Vincenzo F
• Primary Examiner(s): Le, Son
• Assistant Examiner(s): Andrews, Brent J
• Application Number:
  US14/329,661
• Publication Number:
  US 20160013804A1
• Time in Patent Office: 844 Days
• Field of Search: 341/164, 324650-690
• US Class Current: 1/1
• CPC Class Codes: G01R 19/16566 Circuits and arrangements for comparing voltage or current with one or several thresholds and for indicating the result not covered by subgroups G01R19/16504, G01R19/16528, G01R19/16533
• CPC Class Codes: G01R 19/17 giving an indication of the number of times this occurs , i.e. multi-channel analysers
• CPC Class Codes: H03K 5/2481 with at least one differential stage
• CPC Class Codes: H03M 1/34 Analogue value compared with reference values H03M1/48 takes precedence
• CPC Class Codes: H03M 1/60 with intermediate conversion to frequency of pulses

Abstract

In one embodiment, a circuit comprises first and second capacitors configured to receive a sense current in first and second modes, respectively. A comparator is coupled to the first capacitor to compare a voltage of the first capacitor to a reference voltage and generate a count signal in response to the voltage of the first capacitor reaching the reference voltage in the first mode. The comparator is coupled to the second capacitor to compare a voltage of the second capacitor to the reference voltage and generate the count signal in response to the voltage of the second capacitor reaching the reference voltage in the second mode. A reset circuit discharges the first capacitor in the second mode and the second capacitor in the first mode in response to the count signal. A counter increments a count of a number of occurrences of the count signal.

Claims

1. A circuit comprising:

a regulator comprising a pass transistor and a replica transistor, wherein the replica transistor generates a sense current;

a first capacitor configured to receive the sense current in a first mode;

a second capacitor configured to receive the sense current in a second mode, wherein when the first capacitor receives the sense current, the second capacitor does not receive the sense current, and when the second capacitor receives the sense current, the first capacitor does not receive the sense current;

a comparator coupled to the first capacitor to compare a voltage of the first capacitor to a reference voltage and generate a count signal in response to the voltage of the first capacitor reaching the reference voltage in the first mode and coupled to the second capacitor to compare a voltage of the second capacitor to the reference voltage and generate the count signal in response to the voltage of the second capacitor reaching the reference voltage in the second mode;

a reset circuit to discharge the first capacitor in the second mode and to discharge the second capacitor in the first mode in response to the count signal; and

a counter incrementing a count of a number of occurrences of the count signal.

2. The circuit of claim 1 further comprising a switch circuit to couple the first capacitor to the comparator in the first mode and couple the second capacitor to the comparator in the second mode.

3. The circuit of claim 1 wherein the reset circuit comprises a first switch coupled in parallel to the first capacitor and a second switch coupled in parallel to the second capacitor.

4. The circuit of claim 1 wherein the comparator comprises:

a main comparator having an input coupled to the first capacitor and to the second capacitor, the main comparator comparing the voltage on the input to the reference voltage and generating the count signal in response to the voltage on the input reaching the reference voltage; and

an auxiliary comparator that enables the main comparator when the input to the main comparator is within a threshold of the reference voltage.

5. The circuit of claim 1 wherein the comparator comprises:

a main comparator having an input coupled to the first capacitor and to the second capacitor, the main comparator comparing the voltage on the input to the reference voltage and generating the count signal in response to the voltage on the input reaching the reference voltage; and

an auxiliary comparator including an input coupled to the first capacitor and to the second capacitor and including an output to provide an enable signal to the main comparator in response to a comparison of the voltage on the input to a trigger voltage that is less than the reference voltage.

6. The circuit of claim 1 wherein the comparator comprises:

a main comparator having an input coupled to the first capacitor and to the second capacitor, the main comparator comparing the voltage on the input to the reference voltage and generating the count signal in response to the voltage on the input reaching the reference voltage, the main comparator includes a differential input pair and a switch to selectively ground the differential input pair; and

an auxiliary comparator that enables the switch of the main comparator in response to the input to the main comparator being within a threshold of the reference voltage.

7. The circuit of claim 6 wherein the main comparator comprises one or more preamplifiers to increase DC bias of the differential input pair of the main comparator or to amplify the input signal.

8. The circuit of claim 6 wherein the auxiliary comparator comprises a differential input.

9. A circuit comprising:

a regulator comprising a pass transistor and a current source, the current source comprising a replica transistor having a control terminal coupled to a control terminal of the pass transistor;

first means for integrating charge received from the current source in a first mode;

second means for integrating charge received from the current source in a second mode, wherein when the first means for integrating receives charge, the second means for integrating does not receive charge from the current source, and when the second means for integrating receives charge, the first means for integrating does not receive charge from the current source;

means for comparing a voltage of the first means for integrating charge to a reference voltage and generating a count signal in response to the voltage of the first means for integrating charge reaching the reference voltage in the first mode and for comparing a voltage of the second means for integrating charge to the reference voltage and generating the count signal in response to the voltage of the second means for integrating charge reaching the reference voltage in the second mode;

means for counting a number of occurrences of the count signal;

first means for discharging the first means for integrating charge in response to the count signal in the second mode; and

second means for discharging the second means for integrating charge in response to the count signal in the first mode.

10. The circuit of claim 9 wherein the means for comparing comprises:

main means for comparing a voltage on an input thereof that is coupled to the first means for integrating charge and to the second means for integrating charge to the reference voltage and generating the count signal in response to the voltage on the input reaching the reference voltage; and

auxiliary means for comparing the input to the main means to the reference voltage, and if the comparison is within a threshold of the reference voltage, enabling the main means for comparing.

11. The circuit of claim 9 wherein the means for comparing comprises:

main means for comparing a voltage on an input thereof that is coupled to the first means for integrating charge and to the second means for integrating charge to the reference voltage and generating the count signal in response to the voltage on the input reaching the reference voltage; and

auxiliary means for comparing including a differential input pair that triggers at a voltage below the reference voltage to enable the main means for comparing.

12. The circuit of claim 9 wherein the means for comparing comprises:

main means for comparing a voltage on an input thereof that is coupled to the first means for integrating charge and to the second means for integrating charge to the reference voltage and generating the count signal in response to the voltage on the input reaching the reference voltage, the main means for comparing includes a differential input pair and a switch to selectively ground the differential input pair; and

auxiliary means for comparing the input to the main means to the reference voltage, and if the comparison is within a threshold of the reference voltage, enabling the switch of the main means for comparing.

13. The circuit of claim 12 wherein the main means for comparing comprises means for increasing DC bias of the differential input pair of the main means for comparing.

14. The circuit of claim 12 wherein the auxiliary means for comparing comprises a differential input pair.

15. A method comprising:

generating a sense current in a current source of a regulator, the regulator comprising a pass transistor and a replica transistor, wherein the current source comprises the replica transistor and wherein the replica transistor comprises a control terminal coupled to a control terminal of the pass transistor;

storing charge received from the current source in a first capacitor in a first mode;

storing charge received from the current source in a second capacitor in a second mode, wherein when the first capacitor receives charge, the second capacitor does not receive charge from the current source, and when the second capacitor receives charge, the first capacitor does not receive charge from the current source;

discharging the first capacitor in the second mode;

discharging the second capacitor in the first mode;

comparing a voltage of the first capacitor to a reference voltage and generating a count signal in response to the voltage of the first capacitor reaching the reference voltage in the first mode;

comparing a voltage of the second capacitor to the reference voltage and generating the count signal in response to the voltage of the second capacitor reaching the reference voltage in the second mode;

counting a number of occurrences of the count signal; and

switching between the first and second modes in response to the count signal.