Current counting analog-to-digital converter for load current sensing including dynamically biased comparator
First Claim
1. A circuit comprising:
- a regulator comprising a pass transistor and a replica transistor, wherein the replica transistor generates a sense current;
a first capacitor configured to receive the sense current in a first mode;
a second capacitor configured to receive the sense current in a second mode, wherein when the first capacitor receives the sense current, the second capacitor does not receive the sense current, and when the second capacitor receives the sense current, the first capacitor does not receive the sense current;
a comparator coupled to the first capacitor to compare a voltage of the first capacitor to a reference voltage and generate a count signal in response to the voltage of the first capacitor reaching the reference voltage in the first mode and coupled to the second capacitor to compare a voltage of the second capacitor to the reference voltage and generate the count signal in response to the voltage of the second capacitor reaching the reference voltage in the second mode;
a reset circuit to discharge the first capacitor in the second mode and to discharge the second capacitor in the first mode in response to the count signal; and
a counter incrementing a count of a number of occurrences of the count signal.
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Accused Products
Abstract
In one embodiment, a circuit comprises first and second capacitors configured to receive a sense current in first and second modes, respectively. A comparator is coupled to the first capacitor to compare a voltage of the first capacitor to a reference voltage and generate a count signal in response to the voltage of the first capacitor reaching the reference voltage in the first mode. The comparator is coupled to the second capacitor to compare a voltage of the second capacitor to the reference voltage and generate the count signal in response to the voltage of the second capacitor reaching the reference voltage in the second mode. A reset circuit discharges the first capacitor in the second mode and the second capacitor in the first mode in response to the count signal. A counter increments a count of a number of occurrences of the count signal.
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Citations
15 Claims
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1. A circuit comprising:
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a regulator comprising a pass transistor and a replica transistor, wherein the replica transistor generates a sense current; a first capacitor configured to receive the sense current in a first mode; a second capacitor configured to receive the sense current in a second mode, wherein when the first capacitor receives the sense current, the second capacitor does not receive the sense current, and when the second capacitor receives the sense current, the first capacitor does not receive the sense current; a comparator coupled to the first capacitor to compare a voltage of the first capacitor to a reference voltage and generate a count signal in response to the voltage of the first capacitor reaching the reference voltage in the first mode and coupled to the second capacitor to compare a voltage of the second capacitor to the reference voltage and generate the count signal in response to the voltage of the second capacitor reaching the reference voltage in the second mode; a reset circuit to discharge the first capacitor in the second mode and to discharge the second capacitor in the first mode in response to the count signal; and a counter incrementing a count of a number of occurrences of the count signal. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8)
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9. A circuit comprising:
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a regulator comprising a pass transistor and a current source, the current source comprising a replica transistor having a control terminal coupled to a control terminal of the pass transistor; first means for integrating charge received from the current source in a first mode; second means for integrating charge received from the current source in a second mode, wherein when the first means for integrating receives charge, the second means for integrating does not receive charge from the current source, and when the second means for integrating receives charge, the first means for integrating does not receive charge from the current source; means for comparing a voltage of the first means for integrating charge to a reference voltage and generating a count signal in response to the voltage of the first means for integrating charge reaching the reference voltage in the first mode and for comparing a voltage of the second means for integrating charge to the reference voltage and generating the count signal in response to the voltage of the second means for integrating charge reaching the reference voltage in the second mode; means for counting a number of occurrences of the count signal; first means for discharging the first means for integrating charge in response to the count signal in the second mode; and second means for discharging the second means for integrating charge in response to the count signal in the first mode. - View Dependent Claims (10, 11, 12, 13, 14)
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15. A method comprising:
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generating a sense current in a current source of a regulator, the regulator comprising a pass transistor and a replica transistor, wherein the current source comprises the replica transistor and wherein the replica transistor comprises a control terminal coupled to a control terminal of the pass transistor; storing charge received from the current source in a first capacitor in a first mode; storing charge received from the current source in a second capacitor in a second mode, wherein when the first capacitor receives charge, the second capacitor does not receive charge from the current source, and when the second capacitor receives charge, the first capacitor does not receive charge from the current source; discharging the first capacitor in the second mode; discharging the second capacitor in the first mode; comparing a voltage of the first capacitor to a reference voltage and generating a count signal in response to the voltage of the first capacitor reaching the reference voltage in the first mode; comparing a voltage of the second capacitor to the reference voltage and generating the count signal in response to the voltage of the second capacitor reaching the reference voltage in the second mode; counting a number of occurrences of the count signal; and switching between the first and second modes in response to the count signal.
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Specification