Resistive memory with program verify and erase verify capability
First Claim
1. A method of programming a resistive non-volatile memory cell, comprising:
- applying a programming voltage to a first terminal of the resistive non-volatile memory cell;
sensing, during the applying the programming voltage, if the resistive non-volatile memory cell has been programmed;
limiting current through the resistive non-volatile memory cell to a first magnitude; and
after a predetermined time, if the sensing has not detected that the resistive non-volatile memory cell has been programmed, limiting the current through the resistive non-volatile memory cell to a second magnitude greater than the first magnitude,wherein the resistive non-volatile memory cell comprises a programmable resistive element and a switching transistor, the programmable resistive element is coupled to a source line, the switching transistor is coupled to a bit line, and the limiting the current is by coupling a current limiter to the bit line, anderasing the resistive non-volatile memory cell in an erase mode wherein the erasing comprises applying a voltage limit to the bit line and coupling an impedance between the source line and a supply voltage terminal.
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Abstract
A resistive non-volatile memory cell is programmed. A programming voltage is applied to a first terminal of the resistive non-volatile memory cell. Sensing, during the applying the programming voltage, determines if the resistive non-volatile memory cell has been programmed. Current is limited through the resistive non-volatile memory cell to a first magnitude. After a predetermined time, if the sensing has not detected that the resistive non-volatile memory cell has been programmed, the current through the resistive non-volatile memory cell is limited to a second magnitude greater than the first magnitude. The resistive non-volatile memory cell is also erased.
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Citations
17 Claims
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1. A method of programming a resistive non-volatile memory cell, comprising:
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applying a programming voltage to a first terminal of the resistive non-volatile memory cell; sensing, during the applying the programming voltage, if the resistive non-volatile memory cell has been programmed; limiting current through the resistive non-volatile memory cell to a first magnitude; and after a predetermined time, if the sensing has not detected that the resistive non-volatile memory cell has been programmed, limiting the current through the resistive non-volatile memory cell to a second magnitude greater than the first magnitude, wherein the resistive non-volatile memory cell comprises a programmable resistive element and a switching transistor, the programmable resistive element is coupled to a source line, the switching transistor is coupled to a bit line, and the limiting the current is by coupling a current limiter to the bit line, and erasing the resistive non-volatile memory cell in an erase mode wherein the erasing comprises applying a voltage limit to the bit line and coupling an impedance between the source line and a supply voltage terminal. - View Dependent Claims (2, 3, 4, 5, 6)
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7. A method of programming a resistive non-volatile memory cell, comprising:
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applying a programming voltage to a first terminal of the resistive non-volatile memory cell; sensing, during the applying the programming voltage, if the resistive non-volatile memory cell has been programmed; limiting current through the resistive non-volatile memory cell to a first magnitude; and after a predetermined time, if the sensing has not detected that the resistive non-volatile memory cell has been programmed, limiting the current through the resistive non-volatile memory cell to a second magnitude greater than the first magnitude, wherein blocking current through the resistive non-volatile memory cell to ground in response to detecting that, during the applying the programming voltage, the resistive non-volatile memory cell has been programmed.
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8. A method of erasing a resistive non-volatile memory cell, comprising:
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applying a voltage limit to a first terminal of the resistive non-volatile memory cell; coupling an impedance between a second terminal of the resistive non-volatile memory cell and a supply voltage terminal; sensing a state of the memory cell by sensing a voltage on the second terminal of the resistive non-volatile memory cell; and enabling the resistive non-volatile memory cell after the applying the voltage limit and after the coupling the impedance. - View Dependent Claims (9, 10, 11, 12, 13)
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14. A memory, comprising:
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a resistive non-volatile memory cell having an enabling terminal coupled to a word line, a first terminal coupled to a bit line, and a second terminal coupled to a source line; an auto program verify module coupled to the resistive non-volatile memory cell during a program mode that applies a program signal to the resistive non-volatile memory cell, determines if the resistive non-volatile memory cell has been programmed during application of the program signal, terminates application of the program signal in response to a determination that the resistive non-volatile memory cell has been programmed, provides a current limiter that initially provides a limit to the current through the resistive non-volatile memory cell to a first magnitude and increases the limit to the current through the resistive non-volatile memory cell to a second magnitude during the application of the program signal if the program has not occurred after a predetermined time; and an auto erase verify module coupled to the resistive non-volatile memory cell during an erase mode that applies a voltage limit to the resistive non-volatile memory cell and determines if the resistive non-volatile memory cell has been erased while the voltage limit is applied, wherein the auto erase verify module is further characterized by initially enabling the word line during the erase mode after the voltage limit has been applied. - View Dependent Claims (15, 16, 17)
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Specification