Memory device having a different source line coupled to each of a plurality of layers of memory cell arrays

• US 9,564,227 B2
• Filed: 11/10/2015
• Issued: 02/07/2017
• Est. Priority Date: 03/08/2011
• Status: Active Grant

• Current Assignee: Micron Technology, Inc.
• Original Assignee: Micron Technology, Inc.
• Inventors: Goda, Akira, Liu, Zengtao
• Primary Examiner(s): NGUYEN, VAN THU T
• Application Number:
  US14/936,719
• Publication Number:
  US 20160064085A1
• Time in Patent Office: 455 Days
• US Class Current: 1/1
• CPC Class Codes: G11C 11/5642 Sensing or reading circuits; Data output circuits
• CPC Class Codes: G11C 16/0483 comprising cells having several storage transistors connected in series
• CPC Class Codes: G11C 16/10 Programming or data input circuits
• CPC Class Codes: G11C 16/26 Sensing or reading circuits; Data output circuits
• CPC Class Codes: G11C 16/28 using differential sensing or reference cells, e.g. dummy cells
• CPC Class Codes: G11C 5/02 Disposition of storage elements, e.g. in the form of a matrix array
• CPC Class Codes: G11C 5/025 Geometric lay-out considerations of storage- and peripheral-blocks in a semiconductor storage device geometrical lay-out of the components in integrated circuits, H01L27/0207

Abstract

A sensing voltage may be applied to a particular memory cell that is in a particular layer of a plurality of layers of memory cells. While the sensing voltage is applied to the particular memory cell, a source voltage may be applied to an end of a string of memory cells that includes the particular memory cell. The source line voltage may be based on a programming rate of the particular layer.

Claims

1. A method for operating a memory device that comprises a memory array that comprises a plurality of layers of memory cells, the method comprising:

applying a sensing voltage to a particular memory cell that is in a particular layer of the plurality of layers of memory cells; and

applying a source voltage to an end of a string of memory cells that includes the particular memory cell while applying the sensing voltage to the particular memory cell;

wherein the source voltage is based on a programming rate of the particular layer; and

wherein the source voltage being based on the programming rate of the particular layer comprises the source voltage being greater for a slower programming rate of the particular layer than for a faster programming rate of the particular layer.

2. The method of claim 1, wherein applying the source voltage to an end of the string of memory cells comprises activating a select transistor that is coupled between a source and the end of the string of memory cells and applying the source voltage to the source.

3. The method of claim 1, further comprising applying a data line voltage to an opposite end of the string of memory cells while applying the sensing voltage to the particular memory cell.

4. The method of claim 3, wherein the data line voltage is based on the programming rate of the particular layer.

6. The method of claim 3, wherein applying the data line voltage to the opposite end of the string of memory cells comprises activating a select transistor that is coupled between a data line and the opposite end of the string of memory cells and applying the data line voltage to the data line.

7. The method of claim 1, further comprising determining the programming rate of the particular layer.

8. The method of claim 7, wherein determining the programming rate of the particular layer comprises reading the programming rate from a register on the memory device.

9. The method of claim 1, further comprising programming each of the plurality of layers of memory cells and determining a programming rate for each of the plurality of layers of memory cells.

5. A method for operating a memory device that comprises a memory array that comprises a plurality of layers of memory cells, the method comprising:

applying a sensing voltage to a particular memory cell that is in a particular layer of the plurality of layers of memory cells;

applying a source voltage to an end of a string of memory cells that includes the particular memory cell while applying the sensing voltage to the particular memory cell;

applying a data line voltage to an opposite end of the string of memory cells while applying the sensing voltage to the particular memory cell;

wherein the source voltage is based on a programming rate of the particular layer;

wherein the data line voltage is based on the programming rate of the particular layer; and

wherein the data line voltage being based on the programming rate of the particular layer comprises the data line voltage being greater for a slower programming rate of the particular layer than for a faster programming rate of the particular layer.

10. A memory device comprising:

a plurality of layers of memory cells;

wherein the memory device is configured to cause a sensing voltage to be applied to a particular memory cell that is in a particular layer of the plurality of layers of memory cells;

wherein the memory device is configured to cause a source voltage to be applied to an end of a string of memory cells that includes the particular memory cell while applying the sensing voltage to the memory cell;

wherein the source voltage is based on a programming rate of the particular layer; and

wherein the source voltage being based on the programming rate of the particular layer comprises the source voltage being greater for a slower programming rate of the particular layer than for a faster programming rate of the particular layer.

11. The memory device of claim 10, wherein the memory device is configured to cause a data line voltage to be applied to an opposite end of the string of memory cells while the sensing voltage is applied to the particular memory cell.

12. The memory device of claim 11, wherein the data line voltage is based on the programming rate of the particular layer.

13. The memory device of claim 10, wherein the memory device is configured to determine the programming rate of the particular layer.

14. The memory device of claim 10, wherein the memory device is configured to cause the programming rate of the particular layer to be read from a register on the memory device.

15. A memory device comprising:

a stack of layers of memory cells, comprising;

a first plurality of layers of memory cells commonly coupled to a first source;

a second plurality of layers of memory cells commonly coupled to a second source different than the first source; and

respective ones of a plurality of first data lines respectively coupled to respective ones of the first plurality of layers of memory cells and respective ones of a plurality of second data lines respectively coupled to respective ones of the second plurality of layers of memory cells;

wherein the memory device is to bias the first source with a first source voltage and to bias the second source with a second source voltage that is different than the first source voltage;

wherein the memory device is to bias the plurality of first data lines to a first data line voltage and to bias the plurality of second data lines to a second data line voltage different than the first data line voltage; and

wherein a difference between the first data line voltage and the first source voltage is the same as a difference between the second data line voltage and the second source voltage.

16. The memory device of claim 15, wherein the first source voltage is based on a programming rate of the first plurality of layers of memory cells and the second source voltage is based on a programming rate of the second plurality of layers of memory cells.

17. The memory device of claim 15, wherein the first plurality of layers of memory cells comprises a first number of layers of memory cells and the second plurality of layers of memory cells comprises a second number of layers of memory cells, wherein the first number is different than the second number.

18. The memory device of claim 15, wherein the memory device is to apply a sensing voltage to an access line that is commonly coupled to the first plurality of layers of memory cells and the second plurality of layers of memory cells.