Memory device having a different source line coupled to each of a plurality of layers of memory cell arrays
First Claim
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1. A method for operating a memory device that comprises a memory array that comprises a plurality of layers of memory cells, the method comprising:
- applying a sensing voltage to a particular memory cell that is in a particular layer of the plurality of layers of memory cells; and
applying a source voltage to an end of a string of memory cells that includes the particular memory cell while applying the sensing voltage to the particular memory cell;
wherein the source voltage is based on a programming rate of the particular layer; and
wherein the source voltage being based on the programming rate of the particular layer comprises the source voltage being greater for a slower programming rate of the particular layer than for a faster programming rate of the particular layer.
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Abstract
A sensing voltage may be applied to a particular memory cell that is in a particular layer of a plurality of layers of memory cells. While the sensing voltage is applied to the particular memory cell, a source voltage may be applied to an end of a string of memory cells that includes the particular memory cell. The source line voltage may be based on a programming rate of the particular layer.
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Citations
18 Claims
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1. A method for operating a memory device that comprises a memory array that comprises a plurality of layers of memory cells, the method comprising:
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applying a sensing voltage to a particular memory cell that is in a particular layer of the plurality of layers of memory cells; and applying a source voltage to an end of a string of memory cells that includes the particular memory cell while applying the sensing voltage to the particular memory cell; wherein the source voltage is based on a programming rate of the particular layer; and wherein the source voltage being based on the programming rate of the particular layer comprises the source voltage being greater for a slower programming rate of the particular layer than for a faster programming rate of the particular layer. - View Dependent Claims (2, 3, 4, 6, 7, 8, 9)
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5. A method for operating a memory device that comprises a memory array that comprises a plurality of layers of memory cells, the method comprising:
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applying a sensing voltage to a particular memory cell that is in a particular layer of the plurality of layers of memory cells; applying a source voltage to an end of a string of memory cells that includes the particular memory cell while applying the sensing voltage to the particular memory cell; applying a data line voltage to an opposite end of the string of memory cells while applying the sensing voltage to the particular memory cell; wherein the source voltage is based on a programming rate of the particular layer; wherein the data line voltage is based on the programming rate of the particular layer; and wherein the data line voltage being based on the programming rate of the particular layer comprises the data line voltage being greater for a slower programming rate of the particular layer than for a faster programming rate of the particular layer.
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10. A memory device comprising:
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a plurality of layers of memory cells; wherein the memory device is configured to cause a sensing voltage to be applied to a particular memory cell that is in a particular layer of the plurality of layers of memory cells; wherein the memory device is configured to cause a source voltage to be applied to an end of a string of memory cells that includes the particular memory cell while applying the sensing voltage to the memory cell; wherein the source voltage is based on a programming rate of the particular layer; and wherein the source voltage being based on the programming rate of the particular layer comprises the source voltage being greater for a slower programming rate of the particular layer than for a faster programming rate of the particular layer. - View Dependent Claims (11, 12, 13, 14)
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15. A memory device comprising:
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a stack of layers of memory cells, comprising; a first plurality of layers of memory cells commonly coupled to a first source; a second plurality of layers of memory cells commonly coupled to a second source different than the first source; and respective ones of a plurality of first data lines respectively coupled to respective ones of the first plurality of layers of memory cells and respective ones of a plurality of second data lines respectively coupled to respective ones of the second plurality of layers of memory cells; wherein the memory device is to bias the first source with a first source voltage and to bias the second source with a second source voltage that is different than the first source voltage; wherein the memory device is to bias the plurality of first data lines to a first data line voltage and to bias the plurality of second data lines to a second data line voltage different than the first data line voltage; and wherein a difference between the first data line voltage and the first source voltage is the same as a difference between the second data line voltage and the second source voltage. - View Dependent Claims (16, 17, 18)
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Specification