3D semiconductor device and structure

• US 9,564,432 B2
• Filed: 10/08/2014
• Issued: 02/07/2017
• Est. Priority Date: 02/16/2010
• Status: Active Grant

• Current Assignee: Monolithic 3D, Inc.
• Original Assignee: Monolithic 3D, Inc.
• Inventors: Or-Bach, Zvi, Sekar, Deepak C., Cronquist, Brian, Beinglass, Israel, de Jong, Jan Lodewijk
• Primary Examiner(s): GHYKA, ALEXANDER G
• Application Number:
  US14/509,288
• Publication Number:
  US 20150061036A1
• Time in Patent Office: 853 Days
• Field of Search: None
• US Class Current: 1/1
• CPC Class Codes: G11C 17/14 in which contents are determined by selectively establishing, breaking or modifying connecting links by permanently altering the state of coupling elements, e.g. PROM
• CPC Class Codes: H01L 21/76254 with separation/delamination along an ion implanted layer, e.g. Smart-cut, Unibond
• CPC Class Codes: H01L 21/8221 Three dimensional integrated circuits stacked in different levels
• CPC Class Codes: H01L 21/8226 comprising merged transistor logic or integrated injection logic
• CPC Class Codes: H01L 21/84 the substrate being other than a semiconductor body, e.g. being an insulating body
• CPC Class Codes: H01L 2223/5442 comprising non digital, non alphanumeric information, e.g. symbols
• CPC Class Codes: H01L 2223/54426 for alignment
• CPC Class Codes: H01L 2223/54453 for use prior to dicing
• CPC Class Codes: H01L 2224/05599 Material
• CPC Class Codes: H01L 2224/32145 the bodies being stacked
• CPC Class Codes: H01L 2224/45124 Aluminium (Al) as principal constituent
• CPC Class Codes: H01L 2224/45147 Copper (Cu) as principal constituent
• CPC Class Codes: H01L 2224/48091 Arched
• CPC Class Codes: H01L 2224/73265 Layer and wire connectors
• CPC Class Codes: H01L 2224/80001 by connecting a bonding area directly to another bonding area, i.e. connectorless bonding, e.g. bumpless bonding
• CPC Class Codes: H01L 2225/06513 Bump or bump-like direct electrical connections between devices, e.g. flip-chip connection, solder bumps
• CPC Class Codes: H01L 2225/06517 Bump or bump-like direct electrical connections from device to substrate
• CPC Class Codes: H01L 2225/06527 Special adaptation of electrical connections, e.g. rewiring, engineering changes, pressure contacts, layout
• CPC Class Codes: H01L 2225/06541 Conductive via connections through the device, e.g. vertical interconnects, through silicon via [TSV] manufacturing via connections per se H01L21/76898
• CPC Class Codes: H01L 2225/06589 Thermal management, e.g. cooling
• CPC Class Codes: H01L 23/481 : Internal lead connections, e.g. via connections, feedthrough structures
• CPC Class Codes: H01L 23/5252 : comprising anti-fuses, i.e. connections having their state changed from non-conductive to conductive
• CPC Class Codes: H01L 23/528 : Geometry or layout of the interconnection structure H01L27/0207 takes precedence; algorithms G06F30/00
• CPC Class Codes: H01L 23/53214 : the principal metal being aluminium
• CPC Class Codes: H01L 23/53228 : the principal metal being copper
• CPC Class Codes: H01L 23/544 : Marks applied to semiconductor devices or parts, e.g. registration marks, alignment structures, wafer maps test patterns for characterising or monitoring manufacturing processes H01L22/00
• CPC Class Codes: H01L 24/14 : of a plurality of bump connectors
• CPC Class Codes: H01L 24/45 : of an individual wire connector
• CPC Class Codes: H01L 24/48 : of an individual wire connector
• CPC Class Codes: H01L 25/0657 : Stacked arrangements of devices
• CPC Class Codes: H01L 25/18 : the devices being of types provided for in two or more different subgroups of the same main group of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N
• CPC Class Codes: H01L 27/0207 : Geometrical layout of the components, e.g. computer aided design; custom LSI, semi-custom LSI, standard cell technique
• CPC Class Codes: H01L 27/0688 : Integrated circuits having a three-dimensional layout
• CPC Class Codes: H01L 27/0694 : comprising components formed on opposite sides of a semiconductor substrate
• CPC Class Codes: H01L 27/088 : the components being field-effect transistors with insulated gate
• CPC Class Codes: H01L 27/092 : complementary MIS field-effect transistors
• CPC Class Codes: H01L 27/105 : including field-effect components
• CPC Class Codes: H01L 27/11803 : using field effect technology
• CPC Class Codes: H01L 2924/00 : Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/00011 : Not relevant to the scope of the group, the symbol of which is combined with the symbol of this group
• CPC Class Codes: H01L 2924/00012 : Relevant to the scope of the group, the symbol of which is combined with the symbol of this group
• CPC Class Codes: H01L 2924/00014 : the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/01019 : Potassium [K]
• CPC Class Codes: H01L 2924/01066 : Dysprosium [Dy]
• CPC Class Codes: H01L 2924/01322 : Eutectic Alloys, i.e. obtained by a liquid transforming into two solid phases
• CPC Class Codes: H01L 2924/10253 : Silicon [Si]
• CPC Class Codes: H01L 2924/12032 : Schottky diode
• CPC Class Codes: H01L 2924/12036 : PN diode
• CPC Class Codes: H01L 2924/12042 : LASER
• CPC Class Codes: H01L 2924/1301 : Thyristor
• CPC Class Codes: H01L 2924/1305 : Bipolar Junction Transistor [BJT]
• CPC Class Codes: H01L 2924/13062 : Junction field-effect transistor [JFET]
• CPC Class Codes: H01L 2924/13091 : Metal-Oxide-Semiconductor Field-Effect Transistor [MOSFET]
• CPC Class Codes: H01L 2924/14 : Integrated circuits
• CPC Class Codes: H01L 2924/15788 : Glasses, e.g. amorphous oxides, nitrides or fluorides
• CPC Class Codes: H01L 2924/181 : Encapsulation
• CPC Class Codes: H01L 2924/3011 : Impedance
• CPC Class Codes: H01L 2924/3025 : Electromagnetic shielding
• CPC Class Codes: H03K 17/687 : the devices being field-effect transistors
• CPC Class Codes: H03K 19/0948 : using CMOS or complementary insulated gate field-effect transistors
• CPC Class Codes: H03K 19/177 : arranged in matrix form
• CPC Class Codes: H10B 10/00 : Static random access memory [SRAM] devices
• CPC Class Codes: H10B 10/125 : the MOSFET being a thin film transistor [TFT]
• CPC Class Codes: H10B 12/05 : Making the transistor
• CPC Class Codes: H10B 12/053 : the transistor being at least partially in a trench in the substrate vertical transistor in combination with a capacitor formed in a substrate trench H10B12/0383
• CPC Class Codes: H10B 12/50 : Peripheral circuit region structures
• CPC Class Codes: H10B 20/00 : Read-only memory [ROM] devices
• CPC Class Codes: H10B 20/20 : Programmable ROM [PROM] devices comprising field-effect components H10B20/10 takes precedence

Abstract

A semiconductor device, including: a first layer including monocrystalline material and first transistors, the first transistors overlaid by a first isolation layer; a second layer including second transistors and overlaying the first isolation layer, the second transistors including a monocrystalline material; where the second layer includes at least one through layer via to provide connection between at least one of the second transistors and at least one of the first transistors, where the at least one through layer via has a diameter of less than 200 nm; a first set of external connections underlying the first layer to connect the device to external devices; and a second set of external connections overlying the second layer to connect the device to external devices.

Claims

1. A semiconductor device, comprising:

a first layer comprising monocrystalline material and first transistors, said first transistors overlaid by a first isolation layer;

a second layer comprising second transistors and overlaying said first isolation layer, said second transistors comprising a monocrystalline material;

wherein said second layer comprises at least one through layer via to provide connection between at least one of said second transistors and at least one of said first transistors,

wherein said at least one through layer via has a diameter of less than 200 nm;

a first set of external connections underlying said first layer to connect said device to external devices; and

a second set of external connections overlying said second layer to connect said device to external devices.

2. The semiconductor device according to claim 1,

wherein said device comprises connection pads connecting to said second set of external connections, and

wherein at least one of said second transistors is underneath said at least one of said connection pads.

3. The semiconductor device according to claim 1, further comprising:

a back-bias structure for at least one of said second transistors.

4. The semiconductor device according to claim 1,

wherein said second layer comprises a node for wireless connection to external devices.

5. The semiconductor device according to claim 1,

wherein said first set of external connections comprise through-silicon-vias (“

TSV”

).

6. The semiconductor device according to claim 1,

wherein said second transistors comprise a high K dielectric.

7. The semiconductor device according to claim 1,

wherein said second transistors are horizontally oriented transistors and wherein said interconnection layer comprises copper or aluminum.

8. A semiconductor device, comprising:

a first layer comprising monocrystalline material and first transistors, said first transistors overlaid by a first isolation layer;

a second layer comprising second transistors and overlaying said first isolation layer, said second transistors comprising a monocrystalline material,

wherein said second layer comprises at least one through layer via to provide connection between at least one of said second transistors and at least one of said first transistors,

wherein said at least one through layer via has a diameter of less than 250 nm;

a first set of external connections underlying said first layer to connect said device to external devices; and

a second set of external connections overlying said second layer to connect said device to external devices.

9. The semiconductor device according to claim 8,

wherein said device comprises connection pads connecting to said second set of external connections, and

wherein at least one of said second transistors is underneath said at least one of said connection pads.

10. The semiconductor device according to claim 8, further comprising:

a back-bias structure for at least one of said second transistors.

11. The semiconductor device according to claim 8, further comprising:

an interconnection layer in-between said first layer and said second layer,

wherein said interconnection layer comprises copper or aluminum, and

wherein said second transistors are horizontally oriented transistors.

12. The semiconductor device according to claim 8,

wherein said first set of external connections comprise through-silicon-vias (“

TSV”

).

13. The semiconductor device according to claim 8,

wherein said second transistors comprise a high K dielectric.

14. The semiconductor device according to claim 8,

wherein said second layer comprises a node for wireless connection to external devices.

15. A semiconductor device, comprising:

a first layer comprising monocrystalline material and first transistors and first alignment mark, said first transistors overlaid by a first isolation layer;

a second layer comprising second transistors and said second layer is overlaying said first isolation layer, said second transistors comprising a monocrystalline material;

at least one via through said second layer,

wherein said one via is lithographically aligned to said first alignment mark;

a first set of external connections underlying said first layer to connect said device to external devices; and

a second set of external connections overlying said second layer to connect said device to external devices.

16. The semiconductor device according to claim 15,

wherein said device comprises connection pads connecting to said second set of external connections, and

wherein at least one of said second transistors is underneath said at least one of said connection pads.

17. The semiconductor device according to claim 15, further comprising:

a back-bias structure for at least one of said second transistors.

18. The semiconductor device according to claim 15, further comprising:

an interconnection layer in-between said first layer and said second layer,

wherein said interconnection layer comprises copper or aluminum, and

wherein said second transistors are horizontally oriented transistors.

19. The semiconductor device according to claim 15,

wherein said first set of external connections comprise through-silicon-vias (“

TSV”

).

20. The semiconductor device according to claim 15,

wherein said second layer comprises a node for wireless connection to external devices.