Dual-port semiconductor memory and first in first out (FIFO) memory having electrically floating body transistor

• US 9,589,963 B2
• Filed: 12/08/2014
• Issued: 03/07/2017
• Est. Priority Date: 11/16/2010
• Status: Active Grant

• Current Assignee: Zeno Semiconductor, Inc.
• Original Assignee: Zeno Semiconductor, Inc.
• Inventors: Widjaja, Yuniarto
• Primary Examiner(s): Nguyen, Viet Q
• Application Number:
  US14/563,133
• Publication Number:
  US 20150092486A1
• Time in Patent Office: 820 Days
• Field of Search: 365/177, 365/230.05, 365/185.27
• US Class Current: 1/1
• CPC Class Codes: G11C 11/40 using transistors
• CPC Class Codes: G11C 11/403 with charge regeneration common to a multiplicity of memory cells, i.e. external refresh
• CPC Class Codes: G11C 11/405 with three charge-transfer gates, e.g. MOS transistors, per cell
• CPC Class Codes: G11C 7/00 Arrangements for writing information into, or reading information out from, a digital store G11C5/00 takes precedence; auxiliary circuits for stores using semiconductor devices G11C11/4063, G11C11/413
• CPC Class Codes: G11C 8/10 Decoders
• CPC Class Codes: G11C 8/16 Multiple access memory array, e.g. addressing one storage element via at least two independent addressing line groups
• CPC Class Codes: H01L 27/105 including field-effect components
• CPC Class Codes: H01Q 1/2283 mounted in or on the surface of a semiconductor substrate as a chip-type antenna or integrated with other components into an IC package
• CPC Class Codes: H10B 12/10 DRAM devices comprising bipolar components
• CPC Class Codes: H10B 12/20 DRAM devices comprising floating-body transistors, e.g. floating-body cells

Abstract

Multi-port semiconductor memory cells including a common floating body region configured to be charged to a level indicative of a memory state of the memory cell. The multi-port semiconductor memory cells include a plurality of gates and conductive regions interfacing with said floating body region. Arrays of memory cells and method of operating said memory arrays are disclosed for making a memory device.

Claims

1. A semiconductor memory cell comprising:

a plurality of bipolar devices; and

a common base region of a first conductivity type configured to store a charge that is indicative of a memory state of said semiconductor memory cell;

wherein adjacent ones of each of said bipolar devices are separated by a conductive region having a second conductivity type;

wherein said common base region is shared among said plurality of bipolar devices; and

wherein one of said plurality of bipolar devices is configured to maintain the charge stored in said common base region.

2. The semiconductor memory cell of claim 1, wherein said common base region stores at least two stable charge levels.

3. The semiconductor memory cell of claim 1, further comprising a plurality of gates.

4. The semiconductor memory cell of claim 1, wherein the semiconductor memory cell includes ports, wherein a total number of said ports is equal to a total number of said bipolar devices.

5. The semiconductor memory cell of claim 1, wherein the semiconductor memory cell includes a fin structure, and further wherein the fin structure includes the common base region.