Dynamic error vector magnitude compensation
First Claim
1. An electronically-implemented method of biasing a power amplifier, the method comprising:
- selectively charging a capacitor to less than a full amount of charge between successive transmission bursts of the power amplifier based at least partly on an amount of time that the power amplifier is disabled between the successive transmission bursts, said selectively charging including providing a scaled charge current to the capacitor by way of a current mirror;
scaling a reference signal generated from the capacitor with a digital-to-analog converter to provide a scaled reference signal;
generating a bias signal based at least partly on the scaled reference signal; and
biasing the power amplifier with the bias signal such that the power amplifier has a substantially constant gain.
1 Assignment
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Accused Products
Abstract
Aspects of this disclosure relate to compensating for dynamic error vector magnitude. A compensation circuit can generate a compensation signal based at least partly on an amount of time that an amplifier, such as a power amplifier, is turned off between successive transmission bursts of the amplifier. For example, the compensation circuit can charge a capacitor based at least partly on an amount of time that the amplifier is turned off between successive transmission bursts and generate the compensation signal based at least partly on an amount of charge stored on the capacitor. A bias circuit can receive the compensation signal, generate a bias signal based at least partly on the compensation signal, and provide the bias signal to the amplifier to bias the amplifier.
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Citations
21 Claims
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1. An electronically-implemented method of biasing a power amplifier, the method comprising:
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selectively charging a capacitor to less than a full amount of charge between successive transmission bursts of the power amplifier based at least partly on an amount of time that the power amplifier is disabled between the successive transmission bursts, said selectively charging including providing a scaled charge current to the capacitor by way of a current mirror; scaling a reference signal generated from the capacitor with a digital-to-analog converter to provide a scaled reference signal; generating a bias signal based at least partly on the scaled reference signal; and biasing the power amplifier with the bias signal such that the power amplifier has a substantially constant gain. - View Dependent Claims (2, 3, 4, 5)
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6. A power amplifier system comprising:
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a power amplifier configured to receive a bias signal, receive a radio frequency signal, and provide an amplified radio frequency signal; a compensation circuit including (i) a capacitor configured to charge and discharge, (ii) a current mirror configured to provide a scaled down charge current to charge the capacitor, and (iii) a second current mirror configured to provide a scaled down discharge current to discharge the capacitor;
the compensation circuit configured to charge the capacitor for an amount of time corresponding to the power amplifier being turned off between successive transmission bursts of the power amplifier, and the compensation circuit configured to generate a compensation signal based at least partly on an amount of charge stored on the capacitor; anda bias circuit configured to generate the bias signal based at least partly on the compensation signal. - View Dependent Claims (7, 8, 9, 10, 11, 12, 13)
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14. A power amplifier system comprising:
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a power amplifier configured to receive a bias signal, receive a radio frequency signal, and provide an amplified radio frequency signal; a compensation circuit including a capacitor configured to charge and discharge and a current mirror configured to provide a scaled down charge current to charge the capacitor, the compensation circuit configured to charge the capacitor for an amount of time corresponding to the power amplifier being turned off between successive transmission bursts of the power amplifier, and the compensation circuit further including a scaling circuit configured to generate a compensation signal based at least partly on scaling a signal from the capacitor; and a bias circuit configured to generate the bias signal based at least partly on a combination of the compensation signal and a reference signal. - View Dependent Claims (15, 16, 17, 18, 19, 20, 21)
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Specification