Via definition scheme

• US 9,748,133 B2
• Filed: 07/22/2016
• Issued: 08/29/2017
• Est. Priority Date: 09/11/2013
• Status: Active Grant

• Current Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Original Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Inventors: Lu, Yen-Cheng, Shih, Chih-Tsung, Yu, Shinn-Sheng, Chen, Jeng-Horng, Yen, Anthony
• Primary Examiner(s): Harrison, Monica D
• Application Number:
  US15/217,623
• Publication Number:
  US 20160329240A1
• Time in Patent Office: 403 Days
• Field of Search: 257774
• CPC Class Codes: H01L 21/0337 characterised by the process involved to create the mask, e.g. lift-off masks, sidewalls, or to modify the mask, e.g. pre-treatment, post-treatment
• CPC Class Codes: H01L 21/31111 by chemical means
• CPC Class Codes: H01L 21/31122 of layers not containing Si, e.g. PZT, Al2O3
• CPC Class Codes: H01L 21/31144 using masks
• CPC Class Codes: H01L 21/76811 involving multiple stacked pre-patterned masks
• CPC Class Codes: H01L 21/76816 Aspects relating to the layout of the pattern or to the size of vias or trenches layout of the interconnections per se H01L23/528; CAD of ICs G06F30/00
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Abstract

A method includes defining a metal pattern layer over a first dielectric layer. The first dielectric layer is disposed over an etch stop layer and the etch stop layer is disposed over a second dielectric layer. A spacer layer is grown over the metal pattern layer and the first dielectric layer. A metal trench is formed with a metal width in the first dielectric layer. A via hole is formed with a via width in the second dielectric layer.

Claims

1. A method, comprising:

defining a conductive line pattern layer over a first dielectric layer, wherein the first dielectric layer is disposed over a second dielectric layer, and wherein an opening in the conductive line pattern layer exposes a first portion of the first dielectric layer, the first portion having a first width;

forming spacers along sidewalls of the opening, wherein after forming the spacers a second portion of the first dielectric layer is exposed, the second portion of the first dielectric layer having a second width;

etching the second portion of the first dielectric layer using the spacers as a mask to expose a portion of the second dielectric layer;

removing the spacers after etching the second portion of the first dielectric layer, the removing exposing third portions of the first dielectric layer;

etching the third portions of the first dielectric layer to form a trench in the first dielectric layer, the trench having the first width; and

etching the portion of the second dielectric layer to form a via hole in the second dielectric layer, the via hole having the second width.

2. The method of claim 1, wherein forming the spacers comprises forming a spacer layer over the conductive line pattern layer and etching to remove portions of the spacer layer along a bottom of the opening, thereby forming the spacers.

3. The method of claim 2, wherein the conductive line pattern layer comprises an enlarged area and a narrow area, wherein the first portion corresponds to the enlarged area, and wherein the spacer layer fills the narrow area while etching the second portion.

4. The method of claim 2, wherein the spacer layer is grown by an atomic layer deposition (ALD) process.

5. The method of claim 1, wherein the first width is greater than the second width by 10%-50%.

6. The method of claim 1, wherein the second dielectric layer comprises an etch stop layer, and wherein etching the portion of the second dielectric layer comprises etching a third dielectric layer, the etch stop layer being on the third dielectric layer.

7. The method of claim 1, wherein the spacers comprise SiN.

8. An integrated circuit, comprising:

a metal line in a dielectric layer, an upper surface of the metal line being level with an upper surface of the dielectric layer, the upper surface of the metal line having a linear portion and an enlarged area in a plan view, the linear portion of the upper surface of the metal line having a first width along a first direction in the plan view, the enlarged area of the upper surface of the metal line having a second width along a second direction in the plan view, the first direction and the second direction being parallel in the plan view; and

a conductive via extending from the metal line through an underlying dielectric layer, the conductive via being completely below the enlarged area in the plan view.

9. The integrated circuit of claim 8, wherein a width of the enlarged area is 10-50% greater than a width of the linear portion.

10. The integrated circuit of claim 8, wherein a width of the linear portion of the metal line is greater than a width of the conductive via.

11. The integrated circuit of claim 8, wherein the metal line extends through a first dielectric layer and the conductive via extends through a second dielectric layer different than the first dielectric layer.

12. The integrated circuit of claim 11, further comprising an etch stop layer interposed between the first dielectric layer and the second dielectric layer.

13. The integrated circuit of claim 8, wherein the enlarged area has an oval shape.

14. The integrated circuit of claim 8, wherein the enlarged area has a circular shape.

15. An integrated circuit comprising:

one or more dielectric layers;

a metal line extending from a top of the one or more dielectric layers; and

a conductive via extending from the metal line to a bottom of the one or more dielectric layers, wherein a first portion of the metal line directly overlying the conductive via has a width greater than a second portion of the metal line not directly overlying the conductive via, an upper surface of the first portion being level with an upper surface of the second portion, the first portion extending a full width of the metal line, the second portion extending a full with of the metal line.

16. The integrated circuit of claim 15, wherein the one or more dielectric layers comprise:

a first dielectric layer;

an etch stop layer on the first dielectric layer; and

a second dielectric layer on the etch stop layer.

17. The integrated circuit of claim 16, wherein the metal line extends through the first dielectric layer, and wherein the conductive via extends through the etch stop layer and the second dielectric layer.

18. The integrated circuit of claim 15, the width of the first portion is 10%-50% greater than a width of the second portion.

19. The integrated circuit of claim 15, wherein the first portion has an oval shape.

20. The integrated circuit of claim 15, wherein the first portion has a circular shape.