System, method, and computer program product for interfacing one or more storage devices with a plurality of bridge chips

• US 9,792,074 B2
• Filed: 07/06/2009
• Issued: 10/17/2017
• Est. Priority Date: 07/06/2009
• Status: Active Grant

• Current Assignee: Seagate Technology LLC (Seagate Technology Holdings Plc)
• Original Assignee: Seagate Technology LLC (Seagate Technology Holdings Plc)
• Inventors: Stenfort, Ross John, Danilak, Radoslav
• Primary Examiner(s): Alrobaye, Idriss N
• Assistant Examiner(s): TAYLOR, BROOKE JAZMOND
• Application Number:
  US12/498,162
• Publication Number:
  US 20110004710A1
• Time in Patent Office: 3,025 Days
• Field of Search: 710 51
• CPC Class Codes: G06F 3/061 Improving I/O performance
• CPC Class Codes: G06F 3/0661 Format or protocol conversion arrangements
• CPC Class Codes: G06F 3/0674 Disk device

Abstract

A system, method, and computer program product are provided for interfacing one or more storage devices with a plurality of bridge chips. One or more storage devices are provided. Additionally, a plurality of bridge chips are provided. Furthermore, at least one multiplexing device is provided for interfacing the one or more storage devices with the plurality of bridge chips.

Claims

1. An apparatus, comprising:

a plurality of bridge chips collectively at least in part enabling interoperation between a storage device compatible with a first storage protocol and a central processor compatible with a second storage protocol, each of the plurality of bridge chips comprising respective resources comprising one or more protocol translation functions, at least one of the plurality of bridge chips configured to multiplex storage traffic and comprises a plurality of ports organized as a plurality of groups comprising a first port group, a second port group, and a third port group, the first port group being a mass-storage-side port group, the second port group and the third port group being mass-storage-utilizing-side port groups; and

a plurality of communication links enabling each of the plurality of bridge chips to communicate with each other;

wherein performance of a first protocol translation between the storage device and the central processor via a first storage port is at least based upon the resources of a first bridge chip of the plurality of bridge chips, the first bridge chip further comprising the first storage port;

wherein performance of a second protocol translation between the storage device and the central processor via a second storage port is at least based upon the resources of a second bridge chip of the plurality of bridge chips, the second bridge chip further comprising the second storage port;

wherein responsive to a condition in which all resources of a particular one of the plurality of bridge chips are in use, data is distributed across other bridge chips in the plurality of bridge chips;

wherein the at least one of the plurality of bridge chips configured to multiplex storage traffic is enabled to be configured in a first configuration such that information from the storage device presented to the first port group is sent to a selected one of the second port group and the third port group and is further enabled to be configured in a second configuration such that information from the storage device presented to the first port group is sent to the second port group and the third port group;

wherein one of the plurality of bridge chips is connected to one of the plurality of groups of the plurality of ports.

2. The apparatus of claim 1, wherein the storage device comprises one or more storage devices, and the first storage protocol is a Serial Advanced Technology Attachment (SATA) storage protocol.

3. The apparatus of claim 1, wherein each of the plurality of bridge chips are capable of performing at least part of the first protocol translation and the second protocol translation.

4. The apparatus of claim 1, wherein each of the plurality of bridge chips is at least sometimes active at the same time to collectively process storage traffic associated with a selected one of the first storage port and second storage port, and the second storage protocol is a Serial Attached SCSI (SAS) protocol.

5. The apparatus of claim 1, further comprising an interconnect coupling the plurality of bridge chips with the storage device, wherein the interconnect comprises at least one communication link of the plurality of communication links between one or more of the plurality of bridge chips.

6. The apparatus of claim 5, wherein the at least one communication link is configured such that each of the plurality of bridge chips are capable of communicating with each other of the plurality of bridge chips.

7. The apparatus of claim 6, wherein the at least one communication link is configured to be utilized for error recovery.

8. The apparatus of claim 6, wherein the at least one communication link is configured to be utilized for vendor unique communication.

9. The apparatus of claim 1, wherein at least one of the plurality of groups of ports of the at least one of the plurality of bridge chips configured to multiplex storage traffic comprises a plurality of input ports.

10. The apparatus of claim 9, wherein the plurality of input ports are connected to the storage device.

11. The apparatus of claim 1, wherein at least one of the plurality of groups of ports of the at least one of the plurality of bridge chips configured to multiplex storage traffic comprises a plurality of output ports.

12. The apparatus of claim 11, wherein the plurality of output ports are connected to at least one of the plurality of bridge chips.

13. The apparatus of claim 12, wherein a number of the plurality of output ports are divided equally and allocated to each of the plurality of bridge chips.

16. The apparatus of claim 1, wherein the storage traffic is a first storage traffic, wherein a performance of a selected one of a multiplexing of the first storage traffic and a multiplexing of a second storage traffic is based upon a combination of protocol translation resources of the plurality of bridge chips.

14. A method, comprising:

providing interoperation between a storage device compatible with a first storage protocol and a central processor compatible with a second storage protocol;

at least partially implementing storage traffic between the storage device and the central processor via a first storage port using protocol translation resources of a first bridge chip of a plurality of bridge chips, the first bridge chip comprises a plurality of ports organized as a plurality of groups comprising a first port group, a second port group, and a third port group, the first port group being a mass-storage-side port group, the second port group and the third port group being mass-storage-utilizing-side port groups, the first bridge chip further comprising the first storage port;

multiplexing, by the first bridge chip, the storage traffic to at least one of the plurality of bridge chips using protocol translation resources of at least one of the plurality of bridge chips, at least one of the plurality of bridge chips each further comprising a storage port;

communicating between the first bridge chip and at least one of the plurality of bridge chips via a plurality of communication links; and

distributing data across the plurality of bridge chips, at least in part via the plurality of communication links enabling each of the bridge chips to communicate with each other, wherein, responsive to a condition in which all resources of a particular one of the plurality of bridge chips are in use, the data is distributed across other bridge chips in the plurality of bridge chips;

wherein the first bridge chip is enabled to be configured in a first configuration such that information from the storage device presented to the first port group is sent to a selected one of the second port group and the third port group and is further enabled to be configured in a second configuration such that information from the storage device presented to the first port group is sent to the second port group and the third port group;

wherein one of the plurality of bridge chips is connected to one of the plurality of groups of the plurality of ports.

15. The method of claim 14, wherein performance of the multiplexing of the storage traffic is based upon a combination of the protocol translation resources of the plurality of bridge chips.

17. A system comprising:

a storage device;

a first bridge chip and a second bridge chip connected to a multiplexing bridge chip, the first bridge chip and the second bridge chip configured to perform protocol translation functionality and to distribute data, the multiplexing bridge chip configured to multiplex data, to perform protocol translation functionality, and to distribute data, the multiplexing bridge chip comprising a plurality of ports organized as a plurality of groups comprising a first port group, a second port group, and a third port group, the first port group being a mass-storage-side port group, the second port group and the third port group being mass-storage-utilizing-side port groups;

a first output port associated with the first bridge chip;

a second output port associated with the second bridge chip; and

a communication link connecting the storage device to the multiplexing bridge chip;

wherein the multiplexing bridge chip is enabled to be configured in a first configuration such that information from the storage device presented to the first port group is sent to a selected one of the second port group and the third port group and is further enabled to be configured in a second configuration such that information from the storage device presented to the first port group is sent to the second port group and the third port group;

wherein one of the plurality of bridge chips is connected to one of the plurality of groups of the plurality of ports.

18. The system of claim 17, wherein the first bridge chip and the second bridge chip are connected by a second communication link.

19. The system of claim 18, wherein the multiplexing bridge chip is a first multiplexing bridge chip, the first multiplexing bridge chip is connected to a second multiplexing bridge chip by a third communication link, the second multiplexing bridge chip is configured to multiplex data and to perform protocol translations, the first and second multiplexing bridge chip are connected to a multiplexer to perform additional multiplexing functionality.