Propagation of microcode patches to multiple cores in multicore microprocessor
First Claim
1. A microprocessor, comprising:
- a plurality of processing cores, wherein each of the plurality of processing cores executes microcode and comprises hardware to patch the microcode;
wherein a first core of the plurality of processing cores is configured to;
encounter an instruction that instructs the first core to apply a microcode patch; and
in response to encountering the instruction;
inform each core of the other of the plurality of processing cores of the microcode patch; and
apply the microcode patch to the hardware of the first core; and
wherein each core of the plurality of processing cores other than the first core is configured to apply the microcode patch to its hardware in response to being informed by the first core;
wherein none of the plurality of processing cores executes a microcode instruction other than microcode instructions that apply the microcode patch while any of the plurality of processing cores is applying the microcode patch.
1 Assignment
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Accused Products
Abstract
A microprocessor includes a plurality of processing cores, wherein each of the plurality of processing cores executes microcode and comprises hardware to patch the microcode. A first core of the plurality of processing cores is configured to encounter an instruction that instructs the first core to apply a microcode patch. The first core of the plurality of processing cores is further configured to, in response to encountering the instruction, inform each core of the other of the plurality of processing cores of the microcode patch and apply the microcode patch to the hardware of the first core. Each core of the plurality of processing cores other than the first core is configured to apply the microcode patch to the hardware of the core, in response to being informed by the first core.
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Citations
19 Claims
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1. A microprocessor, comprising:
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a plurality of processing cores, wherein each of the plurality of processing cores executes microcode and comprises hardware to patch the microcode; wherein a first core of the plurality of processing cores is configured to; encounter an instruction that instructs the first core to apply a microcode patch; and in response to encountering the instruction; inform each core of the other of the plurality of processing cores of the microcode patch; and apply the microcode patch to the hardware of the first core; and wherein each core of the plurality of processing cores other than the first core is configured to apply the microcode patch to its hardware in response to being informed by the first core; wherein none of the plurality of processing cores executes a microcode instruction other than microcode instructions that apply the microcode patch while any of the plurality of processing cores is applying the microcode patch. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10)
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11. A microprocessor comprising:
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a plurality of processing cores, wherein each of the plurality of processing cores executes microcode and comprises hardware to patch the microcode; a memory shared by the plurality of processing cores; wherein a first core of the plurality of processing cores is configured to; write a microcode patch to the shared memory; encounter an instruction that instructs the first core to apply a microcode patch; and
in response to encountering the instruction;inform each core of the other of the plurality of processing cores of the microcode patch; and apply the microcode patch to the hardware of the first core; wherein each core of the plurality of processing cores other than the first core is configured to apply the microcode patch to its hardware in response to being informed by the first core; wherein to apply the microcode patch, each core of the plurality of processing cores is configured to read the microcode patch from the shared memory. - View Dependent Claims (12)
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13. A method to be performed in a microprocessor having a plurality of processing cores and a shared hardware shared by the plurality of processing cores, wherein each of the plurality of processing cores executes microcode and comprises a private hardware to patch the microcode, the method comprising:
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encountering, by a first core of the plurality of processing cores, an instruction that instructs the first core to apply a microcode patch; in response to said encountering the instruction, applying, by the first core, the microcode patch to the shared hardware; informing, by the first core, each core of the other of the plurality of processing cores of the microcode patch, in response to encountering the instruction; applying, by the first core, the microcode patch to the private hardware of the first core, in response to encountering the instruction; and applying, by each core of the plurality of processing cores other than the first core, the microcode patch to its private hardware, in response to being informed by the first core. - View Dependent Claims (14, 15, 16, 17, 18, 19)
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Specification