Propagation of microcode patches to multiple cores in multicore microprocessor

• US 9,792,112 B2
• Filed: 05/19/2014
• Issued: 10/17/2017
• Est. Priority Date: 08/28/2013
• Status: Active Grant

• Current Assignee: VIA Technologies Incorporated (VIA Technologies)
• Original Assignee: VIA Technologies Incorporated (VIA Technologies)
• Inventors: Henry, G. Glenn, Gaskins, Stephan
• Primary Examiner(s): Pan, Daniel
• Application Number:
  US14/281,786
• Publication Number:
  US 20150067666A1
• Time in Patent Office: 1,247 Days
• Field of Search: 712227, 712248, 717168
• CPC Class Codes: G06F 11/366 using diagnostics G06F11/0703 takes precedence
• CPC Class Codes: G06F 8/654 using techniques specially adapted for alterable solid state memories, e.g. for EEPROM or flash memories
• CPC Class Codes: G06F 8/656 while running
• CPC Class Codes: G06F 9/268 Microinstruction selection not based on processing results, e.g. interrupt, patch, first cycle store, diagnostic programs
• CPC Class Codes: G06F 9/328 for runtime instruction patching
• CPC Class Codes: Y02D 10/00 Energy efficient computing, e.g. low power processors, power management or thermal management

Abstract

A microprocessor includes a plurality of processing cores, wherein each of the plurality of processing cores executes microcode and comprises hardware to patch the microcode. A first core of the plurality of processing cores is configured to encounter an instruction that instructs the first core to apply a microcode patch. The first core of the plurality of processing cores is further configured to, in response to encountering the instruction, inform each core of the other of the plurality of processing cores of the microcode patch and apply the microcode patch to the hardware of the first core. Each core of the plurality of processing cores other than the first core is configured to apply the microcode patch to the hardware of the core, in response to being informed by the first core.

Claims

1. A microprocessor, comprising:

a plurality of processing cores, wherein each of the plurality of processing cores executes microcode and comprises hardware to patch the microcode;

wherein a first core of the plurality of processing cores is configured to;

encounter an instruction that instructs the first core to apply a microcode patch; and

in response to encountering the instruction;

inform each core of the other of the plurality of processing cores of the microcode patch; and

apply the microcode patch to the hardware of the first core; and

wherein each core of the plurality of processing cores other than the first core is configured to apply the microcode patch to its hardware in response to being informed by the first core;

wherein none of the plurality of processing cores executes a microcode instruction other than microcode instructions that apply the microcode patch while any of the plurality of processing cores is applying the microcode patch.

2. The microprocessor of claim 1, wherein each core of the plurality of processing cores other than the first core is configured to apply the microcode patch to its hardware without encountering an instance of the instruction.

3. The microprocessor of claim 1, wherein each of the plurality of processing cores applies the microcode patch while interrupts are disabled on all the plurality of processing cores.

4. The microprocessor of claim 1, wherein the first core is configured to inform each core of the other of the plurality of processing cores of the microcode patch by sending it an interrupt request.

5. The microprocessor of claim 1, wherein each core of the plurality of processing cores other than the first core is configured to transfer control to microcode that applies the microcode patch in response to being informed by the first core.

6. The microprocessor of claim 1, wherein none of the plurality of processing cores executes an architectural instruction while any of the plurality of processing cores is applying the microcode patch.

7. The microprocessor of claim 1, further comprising:

a hardware semaphore shared by the plurality of processing cores; and

wherein the first core is further configured to obtain ownership of the hardware semaphore prior to informing each core of the other of the plurality of processing cores of the microcode patch.

8. The microprocessor of claim 1, further comprising:

an uncore control unit shared by the plurality of processing cores;

wherein each core of the plurality of processing cores is configured to make a synchronization request to the uncore control unit after applying the microcode patch; and

wherein each of the plurality of processing cores is configured to wait to enable interrupts until all of the plurality of processing cores have applied the microcode patch.

9. The microprocessor of claim 1, wherein each of the plurality of processing cores is configured to operate both as the first core and as one of the other of the plurality of processing cores.

10. The microprocessor of claim 1, further comprising:

second hardware to patch the microcode, wherein the second hardware is shared by the plurality of processing cores; and

wherein the first core is further configured to apply the microcode patch to the second hardware in response to encountering the instruction.

11. A microprocessor comprising:

a plurality of processing cores, wherein each of the plurality of processing cores executes microcode and comprises hardware to patch the microcode;

a memory shared by the plurality of processing cores;

wherein a first core of the plurality of processing cores is configured to;

write a microcode patch to the shared memory;

encounter an instruction that instructs the first core to apply a microcode patch; and

in response to encountering the instruction;

inform each core of the other of the plurality of processing cores of the microcode patch; and

apply the microcode patch to the hardware of the first core;

wherein each core of the plurality of processing cores other than the first core is configured to apply the microcode patch to its hardware in response to being informed by the first core;

wherein to apply the microcode patch, each core of the plurality of processing cores is configured to read the microcode patch from the shared memory.

12. The microprocessor of claim 11, further comprising:

an uncore control unit shared by the plurality of processing cores; and

wherein each core of the plurality of processing cores is configured to make a synchronization request to the uncore control unit prior to applying the microcode patch.

13. A method to be performed in a microprocessor having a plurality of processing cores and a shared hardware shared by the plurality of processing cores, wherein each of the plurality of processing cores executes microcode and comprises a private hardware to patch the microcode, the method comprising:

encountering, by a first core of the plurality of processing cores, an instruction that instructs the first core to apply a microcode patch;

in response to said encountering the instruction, applying, by the first core, the microcode patch to the shared hardware;

informing, by the first core, each core of the other of the plurality of processing cores of the microcode patch, in response to encountering the instruction;

applying, by the first core, the microcode patch to the private hardware of the first core, in response to encountering the instruction; and

applying, by each core of the plurality of processing cores other than the first core, the microcode patch to its private hardware, in response to being informed by the first core.

14. The method of claim 13, wherein said applying, by each core of the plurality of processing cores other than the first core, the microcode patch to its private hardware is performed without encountering an instance of the instruction.

15. The method of claim 13, wherein the microcode patch is applied to the private hardware by each of the plurality of processing cores while interrupts are disabled on all the plurality of processing cores.

16. The method of claim 13, wherein none of the plurality of processing cores executes an architectural instruction while any of the plurality of processing cores is applying the microcode patch.

17. The method of claim 13, wherein none of the plurality of processing cores executes a microcode instruction other than microcode instructions that apply the microcode patch while any of the plurality of processing cores is applying the microcode patch.

18. The method of claim 13, wherein the microprocessor also includes an uncore control unit shared by the plurality of processing cores, the method further comprising:

making, by each core of the plurality of processing cores, a synchronization request to the uncore control unit prior to said applying the microcode patch.

19. The method of claim 13, wherein the microprocessor also includes an uncore control unit shared by the plurality of processing cores, the method further comprising:

making, by each core of the plurality of processing cores, a synchronization request to the uncore control unit after said applying the microcode patch; and

waiting, by each of the plurality of processing cores, to enable interrupts until all of the plurality of processing cores have applied the microcode patch.