Thin film transistor, thin film transistor array panel including the same, and manufacturing method thereof

• US 9,793,377 B2
• Filed: 07/24/2015
• Issued: 10/17/2017
• Est. Priority Date: 06/04/2012
• Status: Active Grant

• Current Assignee: Samsung Display Company Limited (Samsung Electronics Co. Ltd.)
• Original Assignee: Samsung Display Company Limited (Samsung Electronics Co. Ltd.)
• Inventors: Lee, Je Hun, Song, Jun Ho, Yeo, Yun Jong, Jung, Hwa Dong
• Primary Examiner(s): ARMAND, MARC ANTHONY
• Application Number:
  US14/808,769
• Publication Number:
  US 20150333154A1
• Time in Patent Office: 816 Days
• CPC Class Codes: H01L 21/02205 the layer being characterised by the precursor material for deposition
• CPC Class Codes: H01L 21/2686 using incoherent radiation
• CPC Class Codes: H01L 21/28247 passivation or protection of the electrode, e.g. using re-oxidation
• CPC Class Codes: H01L 21/3086 characterised by the process involved to create the mask, e.g. lift-off masks, sidewalls, or to modify the mask, e.g. pre-treatment, post-treatment
• CPC Class Codes: H01L 27/1214 comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
• CPC Class Codes: H01L 29/0847 of field-effect transistors with insulated gate H01L29/0653 takes precedence; with a passive supplementary region between source or drain and substrate related to punch-through, capacity or isolation phenomena H01L29/1079; with LDD or DDD structure H01L29/7833; for thin film transistors H01L29/78618
• CPC Class Codes: H01L 29/401 Multistep manufacturing processes
• CPC Class Codes: H01L 29/42356 Disposition, e.g. buried gate electrode H01L29/42324 and H01L29/4234 take precedence
• CPC Class Codes: H01L 29/66742 Thin film unipolar transistors
• CPC Class Codes: H01L 29/66969 of devices having semiconductor bodies not comprising group 14 or group 13/15 materials comprising selenium or tellurium in uncombined form other than as impurities in semiconductor bodies of other materials, comprising cuprous oxide or cuprous iodide H01L21/02365
• CPC Class Codes: H01L 29/7869 having a semiconductor body comprising an oxide semiconductor material, e.g. zinc oxide, copper aluminium oxide, cadmium stannate
• CPC Class Codes: H01L 29/78693 the semiconducting oxide being amorphous
• CPC Class Codes: H01L 29/86 controllable only by variation of the electric current supplied, or only the electric potential applied, to one or more of the electrodes carrying the current to be rectified, amplified, oscillated or switched

Abstract

The present invention relates to a thin film transistor, a thin film transistor array panel, and a manufacturing method thereof. A thin film transistor according to an exemplary embodiments of the present invention includes: a gate electrode; a gate insulating layer positioned on or under the gate electrode; a channel region overlapping the gate electrode, the gate insulating layer interposed between the channel region and the gate electrode; and a source region and a drain region, facing each other with respect to the channel region, positioned in the same layer as the channel region, and connected to the channel region, wherein the channel region, the source region, and the drain region comprise an oxide semiconductor, and wherein a carrier concentration of the source region and the drain region is larger than a carrier concentration of the channel region.

Claims

1. A method of manufacturing a thin film transistor array panel, the method comprising:

forming a gate line comprising a gate electrode on an insulation substrate;

forming a gate insulating layer on the gate electrode;

forming a semiconductor pattern on the gate insulating layer;

forming a linear etch stopper comprising an etch stopper on the semiconductor pattern, the etch stopper intersecting and overlapping the semiconductor pattern;

treating an exposed portion of the semiconductor pattern, thereby forming a source region and a drain region in the exposed portion of the semiconductor pattern; and

forming a data line crossing the gate line,

wherein a carrier concentration of the source region and the drain region is larger than carrier concentration of a channel region, the channel region being a portion of the semiconductor pattern covered by the etch stopper, and

wherein the linear etch stopper extends substantially parallel to the gate line, overlaps the gate line, and crosses the data line in a plan view.

2. The method of claim 1, wherein

treating the semiconductor pattern comprises reducing the semiconductor pattern.

3. The method of claim 1, wherein

forming the etch stopper comprises:

depositing an inorganic material or an organic material on the semiconductor pattern to form an etch stopper layer;

coating a photosensitive film on the etch stopper layer and irradiating light from a rear side of the insulation substrate to form a photosensitive film pattern overlapping the gate electrode; and

etching the etch stopper layer by using the photosensitive film pattern as a mask to form the etch stopper.

4. The method of claim 1, wherein

the treating of the semiconductor pattern includes doping the semiconductor pattern with at least one of fluorine (F), hydrogen (H), and sulfur (S) by using a gas including at least one of tetrafluoromethane (CF₄), nitrogen trifluoride (NF₃), sulfur hexafluoride (SF₆), and methane (CH₄).

5. The method of claim 1, wherein

the carrier concentration of the channel region is less than about 10¹⁸ units/cm³, and the carrier concentration of the source region and the drain region is equal to or more than about 10¹⁸ units/cm³.

6. The method of claim 1, further comprising:

depositing a passivation layer on the channel region, the source region, and the drain region, and

forming an upper gate electrode overlapping the channel region on the passivation layer.

7. The method of claim 1, wherein

forming the etch stopper comprises

depositing an inorganic material or an organic material on the semiconductor pattern to form an etch stopper layer,

coating a photosensitive film on the etch stopper layer and irradiating light from a rear side of the insulation substrate to form a photosensitive film pattern overlapping the gate electrode, and

etching the etch stopper layer by using the photosensitive film pattern as a mask to form the etch stopper.

8. The method of claim 2, wherein

treating the semiconductor pattern comprises doping the semiconductor pattern with at least one of fluorine (F), hydrogen (H), and sulfur (S) by using a gas including at least one of tetrafluoromethane (CF₄), nitrogen trifluoride (NF₃), sulfur hexafluoride (SF₆), and methane (CH₄).

9. The method of claim 3, wherein

the photosensitive film has positive photosensitivity.

10. The method of claim 4, wherein

a concentration of at least one of fluorine (F), hydrogen (H), and sulfur (S) included in the source region and the drain region is equal to or more than about 10¹⁵ units/cm³.

11. The method of claim 7, wherein

the photosensitive film has positive photosensitivity.

12. The method of claim 8, wherein

a concentration of at least one of fluorine (F), hydrogen (H), and sulfur (S) included in the source region and the drain region is equal to or more than about 10¹⁵ units/cm³.

13. The method of claim 12, wherein

the carrier concentration of the channel region is less than about 10¹⁸ units/cm³, and the carrier concentration of the source region and the drain region is equal to or more than about 10¹⁸ units/cm³.

14. The method of claim 13, further comprising:

forming a source electrode and a drain electrode respectively on the source region and the drain region.

15. The method of claim 14, further comprising:

depositing a passivation layer on the channel region, the source region, and the drain region, and

forming an upper gate electrode overlapping the channel region on the passivation layer.

16. A method of manufacturing a thin film transistor array panel, the method comprising:

forming a light blocking pattern on an insulation substrate;

forming a buffer layer on the light blocking pattern and the substrate;

forming a semiconductor pattern comprising an oxide semiconductor on the buffer layer overlapping the light blocking pattern;

depositing an insulating material on the semiconductor pattern to form an insulating material layer;

forming a gate electrode on the insulating material layer;

patterning the insulating material layer by using the gate electrode as an etching mask to form a gate insulating layer and to expose a portion of the semiconductor pattern; and

treating the exposed semiconductor pattern to form a channel region covered by the gate electrode, and to form a source region and a drain region facing each other with respect to the channel region,

wherein a carrier concentration of the source region and the drain region is larger than a carrier concentration of the channel region, wherein

treating the semiconductor pattern includes doping the semiconductor pattern with at least one of fluorine (F), hydrogen (H), and sulfur (S) by using a gas including at least one of tetrafluoromethane (CF₄), nitrogen trifluoride (NF₃), sulfur hexafluoride (SF₆), and methane (CH₄).

17. The method of claim 16, wherein

a concentration of at least one of fluorine (F), hydrogen (H), and sulfur (S) included in the source region and the drain region is equal to or more than about 10¹⁵ units/cm³.