Integrated circuit capacitor including dual gate silicon-on-insulator transistor

• US 9,800,204 B2
• Filed: 03/19/2014
• Issued: 10/24/2017
• Est. Priority Date: 03/19/2014
• Status: Active Grant

• Current Assignee: STMicroelectronics International N.V. (STMicroelectronics NV)
• Original Assignee: STMicroelectronics International N.V. (STMicroelectronics NV)
• Inventors: Kumar, Vinod
• Primary Examiner(s): Parker, Allen
• Assistant Examiner(s): MUSE, ISMAIL A
• Application Number:
  US14/219,786
• Publication Number:
  US 20150270393A1
• Time in Patent Office: 1,315 Days
• Field of Search: None
• CPC Class Codes: G05F 3/16 being semiconductor devices
• CPC Class Codes: H01L 21/84 the substrate being other than a semiconductor body, e.g. being an insulating body
• CPC Class Codes: H01L 29/66181 Conductor-insulator-semiconductor capacitors, e.g. trench capacitors
• CPC Class Codes: H01L 29/7831 with multiple gate structure FinFETs or MuGFETs H01L29/7855, thin film transistors H01L29/78645
• CPC Class Codes: H01L 29/78603 characterised by the insulating substrate or support H01L29/78657 takes precedence
• CPC Class Codes: H01L 29/78648 arranged on opposing sides of the channel
• CPC Class Codes: H01L 29/94 Metal-insulator-semiconductors, e.g. MOS
• CPC Class Codes: H03F 1/0205 in transistor amplifiers
• CPC Class Codes: H03F 2200/451 the amplifier being a radio frequency amplifier
• CPC Class Codes: H03F 3/193 with field-effect devices H03F3/195 takes precedence
• CPC Class Codes: H03K 17/687 the devices being field-effect transistors
• CPC Class Codes: H03L 7/093 using special filtering or amplification characteristics in the loop H03L7/087 - H03L7/091 take precedence

Abstract

Dual gate FD-SOI transistors are used as MOSFET capacitors to replace passive well capacitors in analog microcircuits. Use of the dual gate FD-SOI devices helps to reduce unstable oscillations and improve circuit performance. A thick buried oxide layer within the substrate of an FD-SOI transistor forms a capacitive dielectric that can sustain high operating voltages in the range of 1.2 V-3.3 V, above the transistor threshold voltage. A secondary gate in the FD-SOI transistor is used to create a channel from the back side so that even when the bias voltage on the first gate is small, the effective capacitance remains higher. The capacitance of the buried oxide layer is further utilized as a decoupling capacitor between supply and ground. In one example, a dual gate PMOS FD-SOI transistor is coupled to an operational amplifier and a high voltage output driver to produce a precision-controlled voltage reference generator. In another example, two dual gate PMOS and one dual gate NMOS FD-SOI transistor are coupled to a charge pump, a phase frequency detector, and a current-controlled oscillator to produce a high-performance phase locked loop circuit in which the decoupling capacitor footprint is smaller, in comparison to the conventional usage of passive well capacitance.

Claims

1. A device, comprising:

a silicon-on-insulator substrate including a buried oxide layer over a doped region, the doped region having a first conductivity type;

a dual gate field effect transistor formed on the substrate, the dual gate field effect transistor having a primary gate and a secondary gate, a source region and a drain region, the source and drain regions having a second conductivity type, the second conductivity type being different from the first conductivity type; and

a contact to the doped region having the first conductivity type, the secondary gate of the dual gate field effect transistor formed in the doped region, the contact configured to supply a secondary gate biasing voltage to the doped region,

wherein the source and drain regions are coupled via a source terminal and a drain terminal, respectively, to a voltage supply configured to supply a first voltage, the primary gate is coupled to a biasing voltage supply configured to supply a second voltage that is different than the first voltage, and the secondary gate is coupled to an electrical ground.

2. The device of claim 1, further comprising a primary gate oxide layer underlying the primary gate, wherein the buried oxide layer has a thickness greater than a thickness of the primary gate oxide layer.

3. The device of claim 1 wherein the source and drain regions of the dual gate field effect transistor have respective profiles that are substantially vertical.

4. The device of claim 1 wherein the secondary gate creates a channel between the source and drain regions of the dual gate field effect transistor.

5. The device of claim 1 wherein the secondary gate increases capacitance of the dual gate field effect transistor when operated at a lower bias voltage applied to the primary gate.

6. The device of claim 1 wherein the secondary gate sustains a higher bias voltage than the primary gate.

7. The device of claim 5 wherein capacitance formed by an oxide of the secondary gate is used as a de-coupling capacitor between two supply voltage nodes.

8. The device of claim 1 wherein the dual gate field effect transistor is a PMOS transistor.

9. The device of claim 2 wherein the primary and secondary gates are coupled to different voltages to create capacitance across the gates.

10. The device of claim 2, wherein the biasing voltage supply includes an operational amplifier electrically coupled between the voltage supply and the dual gate field effect transistor, the operational amplifier having inverting and non-inverting input terminals and an output terminal.

11. The device of claim 10, further comprising:

an output transistor coupled to the output terminal;

a voltage divider coupled to the voltage supply and the non-inverting input terminal; and

a current source coupled between the output transistor and the inverting input terminal, the device being operable as a reference voltage generator.

12. The device of claim 1, further comprising:

a loop filter including two dual gate transistors;

a first stage coupled to the loop filter, the first stage operable to receive an input signal at an input frequency; and

a second stage coupled to the loop filter, the second stage operable to produce an output signal at an output frequency, the output signal coupled to the first stage.

13. The device of claim 12 wherein the first stage includes a phase frequency detector and a charge pump and the second stage includes a MOSFET and a current-controlled oscillator, the device being operable as a charge pump phase locked loop circuit.

14. The device of claim 12 wherein the loop filter further includes a de-coupling capacitor in the form of a dual gate transistor.

15. A reference voltage generator circuit, comprising:

a dual gate field effect transistor including;

a substrate including a buried oxide layer formed on a doped region of a first conductivity type, the doped region including a first gate having the first conductivity type;

source and drain regions on the buried oxide layer, the source and drain regions having a second conductivity type, the second conductivity type being different from the first conductivity type;

source and drain terminals respectively coupled to the source and drain regions;

a second gate at least partially overlying the source and drain regions; and

a contact to the first gate having the first conductivity type, the contact configured to couple the doped region to a ground voltage;

a voltage supply coupled to the source and drain regions of the dual gate field effect transistor via the source and drain terminals; and

an operational amplifier having an inverting input terminal, a non-inverting input terminal and an output terminal, the non-inverting input being coupled to the voltage supply, and the output terminal being coupled to the second gate of the dual gate field effect transistor.

16. The reference voltage generator circuit of claim 15, wherein the contact to the first gate is formed on the doped region of a first conductivity type and abuts a side surface of the buried oxide layer.

17. The reference voltage generator circuit of claim 16, the dual gate field effect transistor further including a gate oxide layer underlying the second gate, wherein the buried oxide layer has a thickness greater than a thickness of the gate oxide layer.

20. The reference voltage generator of claim 15 wherein the source and drain regions of the dual gate field effect transistor have respective profiles that are substantially vertical.

18. A charge-pumped phase locked loop circuit, comprising:

an input stage including a phase frequency detector and a charge pump;

an output stage coupled to the input stage and configured to provide a feedback signal to the input stage; and

a filter stage coupled to the input stage, the filter stage including first and second dual gate field effect transistors configured as loop filter capacitors, each of the first and second dual gate field effect transistors including;

a substrate including a buried oxide layer formed on a doped region of a first conductivity type, the doped region including a first gate having the first conductivity type;

source and drain regions on the buried oxide layer, the source and drain regions having a second conductivity type, the second conductivity type being different from the first conductivity type;

a second gate at least partially overlying the source and drain regions; and

a contact to the first gate having the first conductivity type, the contact configured to supply a first gate biasing voltage to the doped region,

wherein the first gates of the first and second dual gate field effect transistors are coupled to a reference voltage, and the second gates of the first and second dual gate field effect transistors are coupled to an output of the input stage.

19. The charge-pumped phase locked loop circuit of claim 18, wherein the filter stage further includes a third dual gate field effect transistor configured to operate as a de-coupling capacitor, the third dual gate field effect transistor including:

a substrate including a buried oxide layer formed on a doped region of a first conductivity type, the doped region including a first gate having the first conductivity type;

source and drain regions on the buried oxide layer, the source and drain regions having a second conductivity type, the second conductivity type being different from the first conductivity type;

a second gate at least partially overlying the source and drain regions; and

a contact to the first gate having the first conductivity type, the contact configured to supply a first gate biasing voltage to the doped region.