Throttling device power

• US 9,891,686 B2
• Filed: 09/26/2013
• Issued: 02/13/2018
• Est. Priority Date: 09/26/2013
• Status: Active Grant

• Current Assignee: Intel Corporation
• Original Assignee: Intel Corporation
• Inventors: Jurski, Janusz, Swanson, Robert, Kumar, Anil, Oriol, Mariusz, Piotrewicz, Waldemar
• Primary Examiner(s): Rahman, Fahmida
• Application Number:
  US14/038,347
• Publication Number:
  US 20150089255A1
• Time in Patent Office: 1,601 Days
• CPC Class Codes: G06F 1/30 Means for acting in the event of power-supply failure or interruption, e.g. power-supply fluctuations for resetting only G06F1/24
• CPC Class Codes: G06F 1/329 by task scheduling
• CPC Class Codes: Y02D 10/00 Energy efficient computing, e.g. low power processors, power management or thermal management

Abstract

An apparatus and system for throttling I/O devices in a computer system is provided. In an example, a method for throttling device power demand during critical power events. The method includes detecting a critical power event and issuing a signal to system devices to defer optional transactions during the critical power event.

Claims

1. A method for throttling device power demand during critical power events, comprising:

detecting a critical power event; and

in response to the detection of the critical power event, issuing a signal from a controller to a peripheral device to defer non-essential transactions including accesses to a main system memory during the critical power event, to indicate a condition of an opportunistic buffer flush and fill (OBFF) state during the critical power event, and to operate out of a local buffer of the peripheral device without accessing any device external to the peripheral device as long as the local buffer is not in an underflow condition, wherein the peripheral device, in response to a local buffer underflow condition during the OBFF state, performs a critical interruption to access the main system memory via a direct memory access operation, wherein the OBFF state allows the peripheral device to continue functioning without shifting to any idle states and wherein the OBFF state does not allow the peripheral device to access system busses except for the critical interruption.

2. The method of claim 1, comprising:

determining if the critical power event has ended, and, if so,

resuming normal operations.

3. The method of claim 1, comprising detecting an underpower event.

4. The method of claim 1, comprising detecting a thermal excursion of a power supply.

5. The method of claim 1, comprising changing a state of a signal line to indicate the opportunistic buffer flush and fill (OBFF) state to system devices.

6. The method of claim 1, comprising deferring non-critical interrupts from system devices.

7. The method of claim 1, comprising deferring non-critical dynamic memory accesses (DMA) from system devices.

8. The method of claim 1, comprising allowing critical interrupts from devices.

9. The method of claim 1, wherein the issuing of the signal to the peripheral device throttles a number of transactions to and from the peripheral device.

10. A system for controlling power usage, comprising:

a power-fault detection system; and

a control system, wherein the control system is configured to;

detect a signal from the power-fault detection system indicating a power fault event; and

in response to detecting the signal from the power-fault detection system, send a signal from the control system to a peripheral device to defer non-essential transactions including accesses to a main system memory during the power fault event, to indicate a condition of an opportunistic buffer flush and fill (OBFF) state during the power fault event, and to operate out of a buffer local to the peripheral device without accessing any device external to the peripheral device as long as the local buffer is not in an underflow condition, wherein the peripheral device, in response to a local buffer underflow condition during the OBFF state, performs a critical interruption to access the main system memory via a direct memory access operation, wherein the OBFF state allows the peripheral device to continue functioning without shifting to any idle states and wherein the OBFF state does not allow the peripheral device to access system busses except for the critical interruption.

11. The system of claim 10, wherein the power-fault detection system comprises a power supply configured to detect a thermal excursion.

12. The system of claim 10, wherein the power-fault detection system is configured to detect a low voltage condition.

13. The system of claim 10, comprising a PCIe bus.

14. The system of claim 10, comprising a signal line coupled to the control system and the peripheral device, wherein the signal line indicates a status of the opportunistic flush and fill (OBFF) state.

15. The system of claim 10, comprising the peripheral device coupled to a signal line, wherein the peripheral device is configured to defer the non-essential transactions based, at least in part, on a voltage level applied to the signal line.

16. The system of claim 10, wherein the peripheral device comprises a graphics processing unit (GPU), a gigabit Ethernet card (GbE), a small computer system interface (SCSI), a central processing unit (CPU), a memory device, a switch, or any combinations thereof.

17. The system of claim 10 comprising a switch configured to receive a throttling message over a communications bus and change a voltage on a signal line in response to the throttling message.

18. A system that throttles back power usage in peripheral devices in a computer system, comprising:

a system management engine comprising;

a power detection system; and

an opportunistic buffer flush and fill (OBFF) controller;

a signal line coupling the OBFF controller to a peripheral device;

a communications bus coupling the OBFF controller to a second peripheral device; and

a module comprising code configured to direct the system management engine to detect a power fault event, and in response to the detection of the power fault event, issue a signal from the controller to the peripheral device to defer non-essential transactions including accesses to a main system memory during the power fault event, and to indicate a condition of an opportunistic buffer flush and fill (OBFF) state during the power fault event, and to operate out of a local buffer of the peripheral device without accessing any device external to the peripheral device as long as the local buffer is not in an underflow condition, wherein the peripheral device, in response to a local buffer underflow condition during the OBFF state, to access the main system memory via a direct memory access operation, wherein the OBFF state allows the peripheral device to continue functioning without shifting to any idle states and wherein the OBFF state does not allow the peripheral device to access system busses except for during the underflow condition.

19. The system of claim 18, wherein the signal indicating the OBFF state comprises a request for a change in a voltage level on the signal line.

20. The system of claim 18, wherein the signal indicating the OBFF state comprises a command sent over the communications bus.

21. The system of claim 18, wherein the communications bus is a PCIe bus.

22. A non-transitory, computer readable medium comprising code configured to control a node manager to throttle device power demand during critical power events, comprising:

code configured to detect a critical power event;

code configured to in, response to the detection of the critical power event, issue a signal from a controller to a peripheral device to defer non-essential transactions including accesses to a main system memory during the critical power event, issue a command over a bus to indicate a condition of an opportunistic buffer flush and fill (OBFF) state during the critical power event, and operate out of a local buffer of the peripheral device without accessing any device external to the peripheral device as long as the local buffer is not in an underflow condition, wherein the peripheral device, in response to a local buffer underflow condition during the OBFF state, performs a critical interruption to access the main system memory via direct memory access operation, wherein the OBFF state allows the peripheral device continue function without shifting to any idle states and wherein the OBFF state does not allow the peripheral device to access system busses except for the critical interruption.

23. The non-transitory, computer readable medium of claim 22, comprising:

code to direct the node manager to determine if the critical power event has ended, and, if so,

code to direct the node manager to resume normal operations.

24. The non-transitory, computer readable medium of claim 22, comprising code to direct the node manager to detect an under-power event.

25. The non-transitory, computer readable medium of claim 22, comprising code to direct the node manager to detect a thermal excursion of a power supply.

26. The non-transitory, computer readable medium of claim 22, comprising code to direct the node manager to change a state of a signal line to indicate the opportunistic buffer flush and fill (OBFF) state to system devices.