Redistribution layer for substrate contacts

• US 9,899,465 B2
• Filed: 07/23/2015
• Issued: 02/20/2018
• Est. Priority Date: 09/25/2014
• Status: Active Grant

• Current Assignee: X Display Company Technology Limited (Sensinnovat BVBA)
• Original Assignee: X-Celeprint Limited
• Inventors: Bower, Christopher, Meitl, Matthew, Cok, Ronald S.
• Primary Examiner(s): Nguyen, Duy T
• Assistant Examiner(s): Jang, Bo Bin
• Application Number:
  US14/807,259
• Publication Number:
  US 20170025593A1
• Time in Patent Office: 943 Days
• Field of Search: None
• CPC Class Codes: G06F 2203/04104 Multi-touch detection in digitiser, i.e. details about the simultaneous detection of a plurality of touching locations, e.g. multiple fingers or pen and finger
• CPC Class Codes: G06F 3/0412 Digitisers structurally integrated in a display
• CPC Class Codes: G06F 3/04164 Connections between sensors and controllers, e.g. routing lines between electrodes and connection pads
• CPC Class Codes: G06F 3/04166 Details of scanning methods, e.g. sampling time, grouping of sub areas or time sharing with display driving Synchronisation with the driving of the display or the backlighting unit to avoid interferences generated internally G06F3/04184
• CPC Class Codes: G06F 3/042 by opto-electronic means
• CPC Class Codes: G06F 3/044 by capacitive means
• CPC Class Codes: H01L 2224/18 High density interconnect [HDI] connectors; Manufacturing methods related thereto
• CPC Class Codes: H01L 25/0753 the devices being arranged next to each other
• CPC Class Codes: H01L 27/156 two-dimensional arrays
• CPC Class Codes: H01L 2933/0066 relating to arrangements for conducting electric current to or from the semiconductor body
• CPC Class Codes: H01L 2933/0075 relating to heat extraction or cooling elements
• CPC Class Codes: H01L 33/58 Optical field-shaping elements
• CPC Class Codes: H01L 33/62 Arrangements for conducting electric current to or from the semiconductor body, e.g. lead-frames, wire-bonds or solder balls
• CPC Class Codes: H01L 33/64 Heat extraction or cooling elements
• CPC Class Codes: H10K 50/87 Arrangements for heating or cooling
• CPC Class Codes: H10K 59/1201 Manufacture or treatment
• CPC Class Codes: H10K 59/131 Interconnections, e.g. wiring lines or terminals
• CPC Class Codes: H10K 59/179 Interconnections, e.g. wiring lines or terminals
• CPC Class Codes: H10K 59/18 Tiled displays
• CPC Class Codes: H10K 59/90 Assemblies of multiple devices comprising at least one organic light-emitting element
• CPC Class Codes: H10K 71/00 : Manufacture or treatment specially adapted for the organic devices covered by this subclass
• CPC Class Codes: H10K 71/80 : using temporary substrates

Abstract

A structure with an interconnection layer for redistribution of electrical connections includes a plurality of first electrical connections disposed on a substrate in a first arrangement. An insulating layer is disposed on the substrate over the first electrical connections. A plurality of second electrical connections is disposed on the insulating layer on a side of the insulating layer opposite the plurality of first electrical connections in a second arrangement. Each second electrical connection is electrically connected to a respective first electrical connection. An integrated circuit is disposed on the substrate and is electrically connected to the first electrical connections. The first electrical connections in the first arrangement have a greater spatial density than the second electrical connections in the second arrangement.

Claims

1. A structure with an interconnection layer for redistribution of electrical connections, comprising:

a substrate having a side;

a plurality of first electrical connections disposed on the side of the substrate in a first arrangement, each of the first electrical connections having a first size;

a single insulating layer comprising a cured material coated on the side of the substrate over the first electrical connections;

a plurality of second electrical connections disposed on the insulating layer in a second arrangement and disposed on a side of the insulating layer opposite the plurality of first electrical connections, each of the second electrical connections having a second size, wherein the second sizes are greater than the first sizes, each second electrical connection of the plurality of second electrical connections electrically connected to a respective first electrical connection through a via having a size corresponding to the first size of the respective first electrical connection and smaller than the second sizes of the plurality of second electrical connections;

a plurality of integrated circuits disposed on the side of the substrate, each electrically connected to a set of the first electrical connections that are more closely spaced within the set on the substrate side than within a corresponding set of the second electrical connections on the insulating layer.

2. The structure of claim 1, wherein one or more vias are located above a corresponding first electrical connection, one or more vias are located below a corresponding second electrical connection, or one or more vias are located above a corresponding first electrical connection and one or more vias are located below a corresponding second electrical connection.

3. The structure of claim 1, wherein one or more micro-wires are located on the same side of the insulating layer as the first electrical connections or one or more micro-wires are located on the same side of the insulating layer as the second electrical contacts, or both.

4. The structure of claim 1, wherein one or more first micro-wires are located on the same side of the insulating layer as the first electrical connections and one or more second micro-wires are located on the same side of the insulating layer as the second electrical contacts and wherein the first micro-wires have a width that is less than the width of the second micro-wires.

5. The structure of claim 1, wherein one or more of the first electrical connections have a first area and one or more of the second electrical connections have a second area greater than the first area.

6. The structure of claim 1, wherein the insulating layer is a black matrix, includes light-absorbing dyes, includes light-absorbing pigments, or is black when exposed to visible light.

7. The structure of claim 1, comprising:

a plurality of micro-wires; and

a plurality of vias in the insulating layer, wherein each second electrical connection of the plurality of second electrical connections is electrically connected to a respective connection of the first electrical connections through a via of the plurality of vias and a micro-wire of the plurality of micro-wires.

8. The structure of claim 7, wherein the micro-wires electrically connect the first electrical connections to the vias.

9. The structure of claim 8, comprising wires electrically connecting the vias to the second electrical connections and wherein the wires are wider than the micro-wires.

10. The structure of claim 1, wherein two or more of the first electrical connections are separated by less than 100 microns and the second electrical connections are separated by at least 100 microns.

11. The structure of claim 1, wherein one of the plurality of integrated circuits has external electrical connections having a spacing equal to or less than a spacing of the first electrical connections in the first arrangement.

12. The structure of claim 1, wherein one of the plurality of integrated circuits is an inorganic light emitter or an inorganic light-emitting diode.

13. The structure of claim 1, wherein the plurality of integrated circuits are in a regular arrangement forming a display.

14. The structure of claim 1, wherein the plurality of integrated circuits comprises a first integrated circuit and a second integrated circuit, wherein the first integrated circuit has external electrical connections spaced apart by a first distance, and the second integrated circuit has external electrical connections spaced apart by a second distance equal to or greater than the first distance.

15. The structure of claim 1, wherein the plurality of integrated circuits comprises a first integrated circuit and the structure comprises a second integrated circuit disposed on the insulating layer and electrically connected to at least one of the second electrical connections and wherein the first integrated circuit electrically communicates with the second integrated circuit.

16. The structure of claim 1, wherein the plurality of integrated circuits comprises a first integrated circuit and the structure comprises a second integrated circuit disposed on the insulating layer and electrically connected to at least one of the second electrical connections and wherein the second integrated circuit electrically controls the first integrated circuit.

17. The structure of claim 1, wherein the substrate is a tile substrate and the structure comprises a backplane substrate and a plurality of tile substrates affixed to the backplane substrate.

18. The structure of claim 17, wherein the plurality of integrated circuits are located between the backplane substrate and the tile substrate.