Semiconductor package and method of fabricating the same

• US 9,922,935 B2
• Filed: 07/29/2016
• Issued: 03/20/2018
• Est. Priority Date: 09/17/2014
• Status: Active Grant

• Current Assignee: Samsung Electronics Co. Ltd.
• Original Assignee: Samsung Electronics Co. Ltd.
• Inventors: Kim, Yeongseok
• Primary Examiner(s): Thai, Luan C
• Application Number:
  US15/223,577
• Publication Number:
  US 20160336275A1
• Time in Patent Office: 599 Days
• Field of Search: 257773
• CPC Class Codes: H01L 21/565 Moulds
• CPC Class Codes: H01L 2223/54433 containing identification or tracking information
• CPC Class Codes: H01L 2223/54486 Located on package parts, e.g. encapsulation, leads, package substrate
• CPC Class Codes: H01L 2224/13101 the principal constituent melting at a temperature of less than 400°C
• CPC Class Codes: H01L 2224/16225 the item being non-metallic, e.g. insulating substrate with or without metallisation
• CPC Class Codes: H01L 2224/2919 with a principal constituent of the material being a polymer, e.g. polyester, phenolic based polymer, epoxy
• CPC Class Codes: H01L 2224/32225 the item being non-metallic, e.g. insulating substrate with or without metallisation
• CPC Class Codes: H01L 2224/45099 Material
• CPC Class Codes: H01L 2224/48091 Arched
• CPC Class Codes: H01L 2224/48227 connecting the wire to a bond pad of the item
• CPC Class Codes: H01L 2224/48472 the other connecting portion not on the bonding area also being a wedge bond, i.e. wedge-to-wedge
• CPC Class Codes: H01L 2224/73204 the bump connector being embedded into the layer connector
• CPC Class Codes: H01L 2224/73265 Layer and wire connectors
• CPC Class Codes: H01L 23/3121 a substrate forming part of the encapsulation
• CPC Class Codes: H01L 23/544 Marks applied to semiconductor devices or parts, e.g. registration marks, alignment structures, wafer maps test patterns for characterising or monitoring manufacturing processes H01L22/00
• CPC Class Codes: H01L 23/562 Protection against mechanical damage H01L23/02, H01L23/28 take precedence
• CPC Class Codes: H01L 24/13 of an individual bump connector
• CPC Class Codes: H01L 24/16 of an individual bump connector
• CPC Class Codes: H01L 24/29 of an individual layer connector
• CPC Class Codes: H01L 24/32 of an individual layer connector
• CPC Class Codes: H01L 24/48 : of an individual wire connector
• CPC Class Codes: H01L 24/73 : Means for bonding being of different types provided for in two or more of groups H01L24/10, H01L24/18, H01L24/26, H01L24/34, H01L24/42, H01L24/50, H01L24/63, H01L24/71
• CPC Class Codes: H01L 2924/00 : Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/00012 : Relevant to the scope of the group, the symbol of which is combined with the symbol of this group
• CPC Class Codes: H01L 2924/00014 : the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/014 : Solder alloys
• CPC Class Codes: H01L 2924/181 : Encapsulation

Abstract

A semiconductor package including a marking film and a method of fabricating the same are provided wherein a marking film including a thermoreactive layer may be applied to a molding layer to protect a semiconductor chip under the molding layer and to efficiently perform a marking process. The thickness of the molding layer may thereby be reduced so the entire thickness of the semiconductor package may be reduced. Also, it is possible to prevent warpage of the semiconductor package through the marking film, provide the surface of the semiconductor package with gloss and freely adjust the color of the surface of the semiconductor package.

Claims

1. A semiconductor package comprising:

a package substrate on which a semiconductor chip is mounted;

a molding layer that covers the package substrate and molds the semiconductor chip; and

a marking film disposed on the molding layer and configured to form a discoloration region in response to a electromagnetic wave,

wherein the marking film comprises a thermoreactive layer which consists of a carbonizable polymer and a carbon black and wherein the thermoreactive layer is exposed to an environment.

2. The semiconductor package of claim 1, wherein the electromagnetic wave includes one of a laser, an ultraviolet ray and a combination of the laser and the ultraviolet ray.

3. The semiconductor package of claim 1, wherein the carbonizable polymer is selected from the group consisting of acrylic, phenolic, epoxy, urethane, polyamide and polyolefin.

4. The semiconductor package of claim 1, wherein the carbonizable polymer is carbonized by reaction with the electromagnetic wave.

5. The semiconductor package of claim 1, wherein the marking film further comprises a reflection layer, the reflection layer including reflectors that reflect the electromagnetic wave.

6. The semiconductor package of claim 5, wherein the reflection layer is formed between the thermoreactive layer and the molding layer.

7. The semiconductor package of claim 1, wherein a thickness of the marking film is between 5 μ

m and 40 μ

m.

8. The semiconductor package of claim 1, wherein a distance between a top surface of the molding layer and a top surface of the semiconductor chip is between 50 μ

m and 150 μ

m.

9. The semiconductor package of claim 1, wherein a distance between a top surface of the molding layer and a top surface of the semiconductor chip is about 1 μ

m to about 40 μ

m.

10. The semiconductor package of claim 5 wherein the reflectors are selected from the group consisting of Sb₂O₃, BaSO₄, (PbCO₃)₂.Pb(OH)₂, TiO₂, ZnO, ZnS, Al₂O₃, SiO₂ and mixtures thereof.

11. A semiconductor package comprising:

a package substrate on which a semiconductor chip is mounted;

a molding layer that covers the package substrate and molds the semiconductor chip; and

a marking film disposed on the molding layer and configured to form a discoloration region in response to a electromagnetic wave,

wherein the marking film includes a thermoreactive layer, the thermoreactive layer consisting of a carbonizable polymer and a carbon black, and the carbonizable polymer is selected from the group consisting of acrylic, phenolic, epoxy, urethane, polyamide and polyolefin, and wherein the thermoreactive layer is exposed to an environment.

12. The semiconductor package of claim 11, wherein the marking film further includes a reflection layer, the reflection layer including reflectors that reflect the electromagnetic wave.

13. The semiconductor package of claim 12, wherein the reflection layer is formed between the thermoreactive layer and the molding layer.

14. The semiconductor package of claim 11, wherein a thickness of the marking film is between 5 μ

m and 40 μ

m.

15. The semiconductor package of claim 11, wherein a distance between a top surface of the molding layer and a top surface of the semiconductor chip is between 50 μ

m and 150 μ

m.

16. The semiconductor package of claim 11, wherein a distance between a top surface of the molding layer and a top surface of the semiconductor chip is about 1 μ

m to about 40 μ

m.

17. A semiconductor package comprising:

a package substrate on which a semiconductor chip is mounted;

a molding layer that covers the package substrate and molds the semiconductor chip; and

a marking film disposed on the molding layer and configured to form a discoloration region in response to a electromagnetic wave,

wherein the marking film comprises a thermoreactive layer and a reflection layer, the thermoreactive layer consisting of a carbonizable polymer and a carbon black and the reflection layer including reflectors that reflect the electromagnetic wave, and

wherein the thermoreactive layer is on the reflection layer such that a top surface of the thermoreactive layer is exposed to an environment.

18. The semiconductor package of claim 17, wherein the reflection layer is formed between the thermoreactive layer and the molding layer.