High speed and high voltage driver
First Claim
1. A high speed high voltage (HSHV) open drain driver comprising:
- a main stack of transistors of a first type coupled between a reference voltage and an output node of the HSHV driver;
a biasing circuit configured to provide biasing voltages to the main stack, the biasing circuit comprising a biasing stack of transistors of a second type;
wherein;
gate nodes of a first to a last transistor of the main stack are coupled sequentially and in a one to one relationship to source and/or drain nodes of a first to a last transistor of the biasing stack,source nodes of transistors of the main stack of transistors are coupled in a one to one relationship to gate nodes of transistors of the biasing stack,the output node is a drain node of an output transistor of the main stack of transistors adapted to be coupled to a high voltage by way of a pull-up element, andtransistors of the main stack and the biasing stack having desired operating voltages substantially smaller than the high voltage.
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Abstract
Systems, methods, and apparatus for biasing a high speed and high voltage driver using only low voltage transistors are described. The apparatus and method are adapted to control biasing voltages to the low voltage transistors such as not to exceed operating voltages of the low voltage transistors while allowing for DC to high speed operation of the driver at high voltage. A stackable and modular architecture of the driver and biasing stages is provided which can grow with a higher voltage requirement of the driver. Capacitive voltage division is used for high speed bias voltage regulation during transient phases of the driver, and resistive voltage division is used to provide bias voltage at steady state. A simpler open-drain configuration is also presented which can be used in pull-up or pull-down modes.
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Citations
21 Claims
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1. A high speed high voltage (HSHV) open drain driver comprising:
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a main stack of transistors of a first type coupled between a reference voltage and an output node of the HSHV driver; a biasing circuit configured to provide biasing voltages to the main stack, the biasing circuit comprising a biasing stack of transistors of a second type; wherein; gate nodes of a first to a last transistor of the main stack are coupled sequentially and in a one to one relationship to source and/or drain nodes of a first to a last transistor of the biasing stack, source nodes of transistors of the main stack of transistors are coupled in a one to one relationship to gate nodes of transistors of the biasing stack, the output node is a drain node of an output transistor of the main stack of transistors adapted to be coupled to a high voltage by way of a pull-up element, and transistors of the main stack and the biasing stack having desired operating voltages substantially smaller than the high voltage. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21)
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Specification