Thin film transistor, manufacturing method thereof, display substrate and display device

• US 10,204,924 B2
• Filed: 11/04/2016
• Issued: 02/12/2019
• Est. Priority Date: 01/12/2016
• Status: Active Grant

• Current Assignee: BOE Technology Group Co., Ltd., Hefei Xinsheng Optoelectric Technology Co. Ltd. (BOE Technology Group Co., Ltd.)
• Original Assignee: BOE Technology Group Co., Ltd., Hefei Xinsheng Optoelectric Technology Co. Ltd. (BOE Technology Group Co., Ltd.)
• Inventors: Su, Tongshang, Zhou, Bin, Wang, Dongfang, Yuan, Guangcai
• Primary Examiner(s): Hall, Victoria K.
• Application Number:
  US15/344,194
• Publication Number:
  US 20170200746A1
• Time in Patent Office: 830 Days
• CPC Class Codes: H01L 21/0273 characterised by the treatment of photoresist layers
• CPC Class Codes: H01L 21/467 using masks
• CPC Class Codes: H01L 27/1225 with semiconductor materials not belonging to the group IV of the periodic table, e.g. InGaZnO
• CPC Class Codes: H01L 27/1229 with different crystal properties within a device or between different devices
• CPC Class Codes: H01L 27/1233 with different thicknesses of the active layer in different devices
• CPC Class Codes: H01L 27/1288 employing particular masking sequences or specially adapted masks, e.g. half-tone mask
• CPC Class Codes: H01L 29/41733 for thin film transistors with insulated gate
• CPC Class Codes: H01L 29/42384 for thin film field effect transistors, e.g. characterised by the thickness or the shape of the insulator or the dimensions, the shape or the lay-out of the conductor
• CPC Class Codes: H01L 29/66969 of devices having semiconductor bodies not comprising group 14 or group 13/15 materials comprising selenium or tellurium in uncombined form other than as impurities in semiconductor bodies of other materials, comprising cuprous oxide or cuprous iodide H01L21/02365
• CPC Class Codes: H01L 29/78609 for preventing leakage current H01L29/78618 takes precedence
• CPC Class Codes: H01L 29/7869 having a semiconductor body comprising an oxide semiconductor material, e.g. zinc oxide, copper aluminium oxide, cadmium stannate
• CPC Class Codes: H01L 29/78696 characterised by the structure of the channel, e.g. multichannel, transverse or longitudinal shape, length or width, doping structure, or the overlap or alignment between the channel and the gate, the source or the drain, or the contacting structure of the channel H01L29/78612 takes precedence; transistors having a drain offset region or a lightly doped drain [LDD] H01L29/78621

Abstract

A thin film transistor (TFT), a manufacturing method thereof, a display substrate and a display device are disclosed. The TFT includes: a gate electrode; a gate insulating layer disposed on the gate electrode; a first active layer disposed on the gate insulating layer; a second active layer disposed on the first active layer, having a length smaller than that of the second active layer; a source electrode disposed on the first active layer, being contacted with a first side of the second active layer; and a drain electrode disposed on the first active layer, being contacted with a second side of the second active layer. Embodiments of the present invention can increase an ON-state current and meanwhile reduce an OFF leakage current in the TFT.

Claims

1. A thin film transistor (TFT), comprising:

a gate electrode;

a gate insulating layer disposed on the gate electrode;

an active layer having a double-layered structure comprising a first active layer disposed directly on the gate insulating layer and a second active layer disposed directly on the first active layer, the second active layer having a length smaller than that of the first active layer, the first active layer comprising a top surface and a bottom surface, the top surface and the bottom surface being parallel to each other, and a first portion of of the top surface being directly in contact with the second active layer;

a source electrode disposed on the first active layer, being partly directly in contact with a second portion of the top surface of the first active layer and partly in contact with a first side surface of the second active layer; and

a drain electrode disposed on the first active layer, being partly directly in contact with a third portion of the top surface of the first active layer and partly in contact with a second side surface of the second active layer, wherein

a resistivity of the first active layer is smaller than that of the second active layer, and

the first portion, the second portion, and the third portion of the top surface of the first active layer are continuously and integrally formed to have an equal height everywhere along the top surface.

2. The TFT according to claim 1, wherein a material of both the first active layer and the second active layer is indium gallium zinc oxide (IGZO).

3. The TFT according to claim 2, wherein a content of indium in the second active layer is smaller than that in the first active layer.

4. The TFT according to claim 1, wherein a perpendicular bisector of the second active layer is coincident with that of the first active layer.

5. The TFT according to claim 2, wherein a perpendicular bisector of the second active layer is coincident with that of the first active layer.

6. The TFT according to claim 3, wherein a perpendicular bisector of the second active layer is coincident with that of the first active layer.

7. A display substrate, comprising the thin film transistor according to claim 1.

8. A manufacturing method of TFT, comprising:

forming a gate electrode on a substrate;

forming a gate insulating layer on the gate electrode;

forming an active layer having a double-layered structure, by directly forming a first active layer on the gate insulating layer and directly forming a second active layer on the first active layer, the second active layer having a length smaller than that of the first active layer, the first active layer comprising a top surface and a bottom surface, the top surface and the bottom surface being parallel to each other, and a first portion of the top surface being directly in contact with the second active layer; and

forming a source electrode and a drain electrode on the top surface of the first active layer, the source electrode and the drain electrode being partly directly in contact with a second portion and a third portion of the top surface of the first active layer, respectively, and the source electrode and the drain electrode being partly in contact with two opposing sides of the second active layer, respectively, wherein

a resistivity of the first active layer is smaller than that of the second active layer, and

the first portion, the second portion, and the third portion of the top surface of the first active layer are continuously and integrally formed to have an equal height everywhere along the top surface.

9. The manufacturing method of claim 8, wherein forming the first active layer and the second active layer comprises:

forming a first semiconductor material layer on the gate insulating layer;

forming a second semiconductor material layer on the first semiconductor material layer;

forming a photoresist on the second semiconductor material layer;

etching the photoresist by using a halftone mask to completely remove a portion of the photoresist in a first region, partly remove a portion of the photoresist in a second region, and preserve a portion of the photoresist in a third region;

etching away a portion of the first semiconductor material layer in the first region and a portion of the second semiconductor material layer in the first region so that a remaining portion of the first semiconductor material layer is the first active layer;

etching away a remaining portion of the photoresist in the second region; and

etching away a portion of the second semiconductor material layer in the second region so that a remaining portion of the second semiconductor material layer is the second active layer.

10. The manufacturing method of claim 9, wherein forming the first semiconductor material layer and the second semiconductor material layer comprises:

sputtering a first target of indium gallium zinc oxide (IGZO) to form the first semiconductor material layer; and

sputtering a second target of indium gallium zinc oxide (IGZO) to form the second semiconductor material layer.

11. The manufacturing method of claim 10, wherein forming the first semiconductor material layer comprises sputtering the first target of indium gallium zinc oxide (IGZO) on the gate insulating layer at a first power, wherein forming the second semiconductor material layer comprises sputtering the second target of indium gallium zinc oxide (IGZO) on the first semiconductor material layer at a second power, and wherein the first target and the second target have a same content of indium, and the second power is larger than the first power.