Semiconductor device and method of manufacturing the same

• US 10,249,604 B2
• Filed: 03/12/2015
• Issued: 04/02/2019
• Est. Priority Date: 08/13/2014
• Status: Active Grant

• Current Assignee: Samsung Electronics Co. Ltd.
• Original Assignee: Samsung Electronics Co. Ltd.
• Inventors: Chu, Kunmo, Moon, Changyoul, Lee, Sunghee, Hwang, Junsik
• Primary Examiner(s): Parekh, Nitin
• Application Number:
  US14/656,298
• Publication Number:
  US 20160049564A1
• Time in Patent Office: 1,482 Days
• Field of Search: 257 99, 257750, 257762
• CPC Class Codes: H01L 21/78 with subsequent division of the substrate into plural individual devices cutting to change the surface-physical characteristics or shape of semiconductor bodies H01L21/304
• CPC Class Codes: H01L 2224/04026 Bonding areas specifically adapted for layer connectors
• CPC Class Codes: H01L 2224/05666 Titanium [Ti] as principal constituent
• CPC Class Codes: H01L 2224/05671 Chromium [Cr] as principal constituent
• CPC Class Codes: H01L 2224/131 with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
• CPC Class Codes: H01L 2224/16225 the item being non-metallic, e.g. insulating substrate with or without metallisation
• CPC Class Codes: H01L 2224/24146 the HDI interconnect connecting to the same level of the lower semiconductor or solid-state body at which the upper semiconductor or solid-state body is mounted
• CPC Class Codes: H01L 2224/29082 Two-layer arrangements
• CPC Class Codes: H01L 2224/29083 Three-layer arrangements
• CPC Class Codes: H01L 2224/29111 Tin [Sn] as principal constituent
• CPC Class Codes: H01L 2224/29139 Silver [Ag] as principal constituent
• CPC Class Codes: H01L 2224/29155 Nickel [Ni] as principal constituent
• CPC Class Codes: H01L 2224/32145 the bodies being stacked
• CPC Class Codes: H01L 2224/32503 comprising an intermetallic compound
• CPC Class Codes: H01L 2224/33181 On opposite sides of the body
• CPC Class Codes: H01L 2224/45099 Material
• CPC Class Codes: H01L 2224/48225 the item being non-metallic, e.g. insulating substrate with or without metallisation
• CPC Class Codes: H01L 2224/73204 the bump connector being embedded into the layer connector
• CPC Class Codes: H01L 2224/73217 Layer and HDI connectors
• CPC Class Codes: H01L 2224/73227 Wire and HDI connectors
• CPC Class Codes: H01L 2224/73253 : Bump and layer connectors
• CPC Class Codes: H01L 2224/73259 : Bump and HDI connectors
• CPC Class Codes: H01L 2224/73265 : Layer and wire connectors
• CPC Class Codes: H01L 2224/73267 : Layer and HDI connectors
• CPC Class Codes: H01L 2224/81 : using a bump connector
• CPC Class Codes: H01L 2224/82101 : by additive methods, e.g. direct writing
• CPC Class Codes: H01L 2224/83 : using a layer connector
• CPC Class Codes: H01L 2224/83005 : being a temporary or sacrificial substrate
• CPC Class Codes: H01L 2224/83193 : wherein the layer connectors are disposed on both the semiconductor or solid-state body and another item or body to be connected to the semiconductor or solid-state body
• CPC Class Codes: H01L 2224/83204 : with a graded temperature profile
• CPC Class Codes: H01L 2224/8381 : involving forming an intermetallic compound at the bonding interface
• CPC Class Codes: H01L 2224/83825 : Solid-liquid interdiffusion
• CPC Class Codes: H01L 2224/83948 : Thermal treatments, e.g. annealing, controlled cooling
• CPC Class Codes: H01L 2224/92 : Specific sequence of method steps
• CPC Class Codes: H01L 2224/9202 : Forming additional connectors after the connecting process
• CPC Class Codes: H01L 2224/92144 : the second connecting process involving a build-up interconnect
• CPC Class Codes: H01L 2224/92244 : the second connecting process involving a build-up interconnect
• CPC Class Codes: H01L 2224/94 : at wafer-level, i.e. with connecting carried out on a wafer comprising a plurality of undiced individual devices
• CPC Class Codes: H01L 2225/06517 : Bump or bump-like direct electrical connections from device to substrate
• CPC Class Codes: H01L 23/481 : Internal lead connections, e.g. via connections, feedthrough structures
• CPC Class Codes: H01L 24/05 : of an individual bonding area
• CPC Class Codes: H01L 24/13 : of an individual bump connector
• CPC Class Codes: H01L 24/16 : of an individual bump connector
• CPC Class Codes: H01L 24/24 : of an individual high density interconnect connector
• CPC Class Codes: H01L 24/29 : of an individual layer connector
• CPC Class Codes: H01L 24/32 : of an individual layer connector
• CPC Class Codes: H01L 24/33 : of a plurality of layer connectors
• CPC Class Codes: H01L 24/48 : of an individual wire connector
• CPC Class Codes: H01L 24/73 : Means for bonding being of different types provided for in two or more of groups H01L24/10, H01L24/18, H01L24/26, H01L24/34, H01L24/42, H01L24/50, H01L24/63, H01L24/71
• CPC Class Codes: H01L 24/82 : by forming build-up interconnects at chip-level, e.g. for high density interconnects [HDI] interconnection structure between a plurality of semiconductor chips H01L23/5389
• CPC Class Codes: H01L 24/83 : using a layer connector
• CPC Class Codes: H01L 24/92 : Specific sequence of method steps
• CPC Class Codes: H01L 24/94 : at wafer-level, i.e. with connecting carried out on a wafer comprising a plurality of undiced individual devices
• CPC Class Codes: H01L 25/0657 : Stacked arrangements of devices
• CPC Class Codes: H01L 25/50 : Multistep manufacturing processes of assemblies consisting of devices, each device being of a type provided for in group H01L27/00 or H01L29/00 H01L21/50 takes precedence
• CPC Class Codes: H01L 2924/00014 : the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/014 : Solder alloys
• CPC Class Codes: H01L 2924/10253 : Silicon [Si]
• CPC Class Codes: H01L 2924/1033 : Gallium nitride [GaN]
• CPC Class Codes: H01L 2924/12041 : LED
• CPC Class Codes: H01L 2924/12042 : LASER
• CPC Class Codes: H01L 2924/1461 : MEMS
• CPC Class Codes: H01L 2924/15311 : being a ball array, e.g. BGA
• CPC Class Codes: H01L 2924/181 : Encapsulation
• CPC Class Codes: H01L 2924/3512 : Cracking
• CPC Class Codes: H01L 2933/0066 : relating to arrangements for conducting electric current to or from the semiconductor body
• CPC Class Codes: H01L 33/0093 : Wafer bonding; Removal of the growth substrate

Abstract

A semiconductor device includes a base substrate and a semiconductor chip on the base substrate, the semiconductor chip including a first layer structure and a second layer structure opposite to the first layer structure, at least one of the first and second layer structures including a semiconductor device portion, and a bonding structure between the first layer structure and the second layer structure, the bonding structure including a silver-tin (Ag—Sn) compound and a nickel-tin (Ni—Sn) compound.

Claims

1. A semiconductor device comprising:

a base substrate; and

a semiconductor chip on the base substrate, the semiconductor chip being an individual semiconductor chip, the semiconductor chip including;

a first layer structure and a second layer structure opposite to the first layer structure, the second layer structures is a semiconductor device portion, and

a bonding structure between the first layer structure and the second layer structure, the bonding structure including a silver-tin (Ag—

Sn) compound portion and a nickel-tin (Ni—

Sn) compound portion above and below the Ag—

Sn compound portion, the Ag—

Sn compound portion and the Ni—

Sn compound portion having a same width in a horizontal direction such that edge portions of the Ag—

Sn compound portion are exposed and edge portions of the Ni—

Sn compound portion are exposed,

wherein the first layer structure is a chip substrate including a semiconductor substrate,

wherein the chip substrate including the semiconductor substrate is between the base substrate and the semiconductor device portion, and

wherein the individual semiconductor chip includes the chip substrate, the semiconductor device portion and the bonding structure between the chip substrate and the semiconductor device portion.

2. The semiconductor device of claim 1, wherein the bonding structure further includes pure Ni.

3. The semiconductor device of claim 1, wherein

the Ag—

Sn compound portion includes Ag₃Sn, and

the Ni—

Sn compound portion includes Ni₃Sn₄.

4. The semiconductor device of claim 3, wherein the bonding structure includes

an intermediate layer including the Ag₃Sn portion and the Ni₃Sn₄ portion,

a first Ni layer between the intermediate layer and the first layer structure, and

a second Ni layer between the intermediate layer and the second layer structure.

5. The semiconductor device of claim 3, wherein the Ni—

Sn compound portion further includes Ni₃Sn.

6. The semiconductor device of claim 1, wherein an Ag content in the bonding structure is about 0.5 wt % to about 23.1 wt %.

7. The semiconductor device of claim 1, wherein the semiconductor device portion includes a light-emitting device portion.

8. The semiconductor device of claim 7, wherein

the first layer structure includes a silicon (Si) substrate,

the second layer structure includes the light-emitting device portion, and

the light-emitting device portion includes a Group III-V semiconductor.

9. The semiconductor device of claim 1, wherein

the first layer structure includes a first substrate and a first semiconductor device portion on the first substrate, and

the second layer structure includes a second substrate and a second semiconductor device portion on the second substrate.

10. The semiconductor device of claim 1, wherein at least one third layer structure is bonded onto the second layer structure.

11. The semiconductor device of claim 1, wherein a die shear strength of the bonding structure is 32 MPa or more.

12. The semiconductor device of claim 1, wherein a re-melting temperature of the bonding structure is 350 deg. C. or more.

13. The semiconductor device of claim 1, wherein an average elastic modulus of both the Ag—

Sn compound portion and the Ni—

Sn compound portion is 124 GPa to 152 GPa.

14. The semiconductor device of claim 1, wherein an average hardness of both the Ag—

Sn compound portion and the Ni—

Sn compound portion is 4.5 GPa to 9 GPa as measured by a Vickers hardness scale.

15. A semiconductor chip, the semiconductor chip comprising:

a bonding layer between a first layer structure and a second layer structure, the bonding layer including a silver-tin (Ag—

Sn) compound portion and a nickel-tin (Ni—

Sn) compound portion above and below the Ag—

Sn compound portion, the Ag—

Sn compound portion and the Ni—

Sn compound portion having a same width in a horizontal direction such that edge portions of the Ag—

Sn compound portion are exposed and edge portions of the Ni—

Sn compound portion are exposed,

wherein the semiconductor chip is an individual semiconductor chip,

wherein the first layer structure is a chip substrate including a semiconductor substrate, and the second layer structure is a semiconductor device portion, and

wherein the individual semiconductor chip includes the chip substrate, the semiconductor device portion and the bonding layer between the chip substrate and the semiconductor device portion.

16. The semiconductor chip of claim 15, wherein

the Ag—

Sn compound portion includes Ag₃Sn, and

the Ni—

Sn compound portion includes Ni₃Sn₄.

17. The semiconductor chip of claim 16, wherein the Ni—

Sn compound portion further includes Ni₃Sn.

18. The semiconductor chip of claim 16, wherein the bonding layer includes

an intermediate layer including the Ag₃Sn portion and the Ni₃Sn₄ portion,

a first layer on a first side of the intermediate layer, the first layer including pure Ni, and

a second layer on a second side of the intermediate layer, the second layer including pure Ni.

19. The semiconductor chip of claim 15, wherein an Ag content in the bonding layer is about 0.5 wt % to about 23.1 wt %.

20. The semiconductor chip of claim 15, wherein

the first layer structure includes a first substrate and a first semiconductor device portion on the first substrate, and

the second layer structure includes a second substrate and a second semiconductor device portion on the second substrate.

21. A semiconductor device comprising:

a base substrate;

a semiconductor chip on the base substrate, the semiconductor chip being an individual semiconductor chip, the semiconductor chip including;

a first layer structure and a second layer structure opposite to the first layer structure, at least one of the first and second layer structures including a semiconductor device portion, and

a bonding structure between the first layer structure and the second layer structure, the bonding structure including a silver-tin (Ag—

Sn) compound portion and a nickel-tin (Ni—

Sn) compound portion above and below the Ag—

Sn compound portion; and

a filling material between the base substrate and the semiconductor chip,

wherein the bonding structure is spaced apart from the filling material and no portion of the bonding structure contacts the filling material;

wherein the first layer structure is a chip substrate including a semiconductor substrate, and the second layer structure is the semiconductor device portion,

wherein the chip substrate including the semiconductor substrate is between the filling material and the semiconductor device portion, and

wherein the individual semiconductor chip includes the chip substrate, the semiconductor device portion and the bonding structure between the chip substrate and the semiconductor device portion.