Memory cells including vertical nanowire transistors
First Claim
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1. A circuit, comprising:
- an SRAM cell, the SRAM cell comprising a set of vertical nanowire transistor columns, each member of the set including a vertical nanowire transistor, and at least one member of the set being a vertical nanowire transistor column including a first vertical nanowire transistor on top of and connected in series to a second vertical nanowire transistor.
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Abstract
A circuit including an SRAM cell with a set of vertical nanowire transistor columns is provided. Each member of the set includes a vertical nanowire transistor and at least one member of the set is a vertical nanowire transistor column including two vertical nanowire transistors in series. The set can consist of four vertical nanowire transistor columns, a first column including two n-type vertical nanowire transistors, a second column including two n-type vertical nanowire transistors, a third column including one p-type vertical nanowire transistor and a fourth column including one p-type vertical nanowire transistor. EDA tools for such circuits are also provided.
115 Citations
36 Claims
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1. A circuit, comprising:
an SRAM cell, the SRAM cell comprising a set of vertical nanowire transistor columns, each member of the set including a vertical nanowire transistor, and at least one member of the set being a vertical nanowire transistor column including a first vertical nanowire transistor on top of and connected in series to a second vertical nanowire transistor. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11)
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12. A computer system adapted to process a computer implemented representation of a circuit design, comprising:
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a processor and memory coupled to the processor, the memory storing instructions executable by the processor, including instructions to select cells from a cell library and/or to compile a memory layout using a selected cell; the cell library including entries for a plurality of cells, entries in the cell library including specifications of particular cells in a computer executable language; and at least one entry in the cell library, or the selected cell, comprising a specification of physical structures and timing parameters of an SRAM cell, the SRAM cell comprising a set of vertical nanowire transistor columns, each member of the set including a vertical nanowire transistor, and at least one member of the set being a vertical nanowire transistor column including a first vertical nanowire transistor on top of and connected in series to a second vertical nanowire transistor. - View Dependent Claims (13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23)
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24. A computer program product, comprising:
a memory device having stored thereon a machine readable specification of a cell, the specification of the cell including computer readable parameters specifying structural features of a physical implementation of a circuit, the specification being executable by a computer running a placement process to control physical placement of the circuit with other circuits or components or for use by a memory compiler to compile a memory array using the cell, the circuit including; an SRAM cell, the SRAM cell comprising a set of vertical nanowire transistor columns, each member of the set including a vertical nanowire transistor, and at least one member of the set being a vertical nanowire transistor column including a first vertical nanowire transistor on top of and connected in series to a second vertical nanowire transistor. - View Dependent Claims (25, 26, 27, 28, 29, 30, 31, 32, 33, 34, 35)
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36. A circuit, comprising:
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an SRAM cell, the SRAM cell comprising a set of vertical nanowire transistor columns, each member of the set including a vertical nanowire transistor, and at least one member of the set being a vertical nanowire transistor column including two vertical nanowire transistors in series, wherein the set consists of four vertical nanowire transistor columns, a first column including two n-type vertical nanowire transistors, a second column including two n-type vertical nanowire transistors, a third column including one p-type vertical nanowire transistor and a fourth column including one p-type vertical nanowire transistor.
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Specification