MEMORY CELLS INCLUDING VERTICAL NANOWIRE TRANSISTORS

• US 20180122793A1
• Filed: 10/20/2017
• Published: 05/03/2018
• Est. Priority Date: 10/28/2016
• Status: Active Grant

• Current Assignee: Synopsys Incorporated
• Original Assignee: Synopsys Incorporated
• Inventors: Moroz, Victor, Kawa, Jamil, Nguyen, Thu
• Granted Patent: US 10,312,229 B2
• Time in Patent Office: Days
• CPC Class Codes: G06F 30/392 Floor-planning or layout, e.g. partitioning or placement
• CPC Class Codes: H01L 21/823885 with a particular manufacturing method of vertical transistor structures, i.e. with channel vertical to the substrate surface with a current flow parallel to the substrate surface H01L21/823821
• CPC Class Codes: H01L 23/535 including internal interconnections, e.g. cross-under constructions internal lead connections H01L23/481
• CPC Class Codes: H01L 27/0207 Geometrical layout of the components, e.g. computer aided design; custom LSI, semi-custom LSI, standard cell technique
• CPC Class Codes: H01L 27/0688 Integrated circuits having a three-dimensional layout
• CPC Class Codes: H01L 29/0676 oriented perpendicular or at an angle to a substrate
• CPC Class Codes: H01L 29/4238 characterised by the surface lay-out
• CPC Class Codes: H01L 29/42392 fully surrounding the channel, e.g. gate-all-around
• CPC Class Codes: H01L 29/66439 with a one- or zero-dimensional channel, e.g. quantum wire FET, in-plane gate transistor [IPG], single electron transistor [SET], striped channel transistor, Coulomb blockade transistor with an active layer made of a group 13/15 material H01L29/66469
• CPC Class Codes: H01L 29/775 with one dimensional charge carrier gas channel, e.g. quantum wire FET
• CPC Class Codes: H01L 29/78642 Vertical transistors
• CPC Class Codes: H01L 29/78696 characterised by the structure of the channel, e.g. multichannel, transverse or longitudinal shape, length or width, doping structure, or the overlap or alignment between the channel and the gate, the source or the drain, or the contacting structure of the channel H01L29/78612 takes precedence; transistors having a drain offset region or a lightly doped drain [LDD] H01L29/78621
• CPC Class Codes: H10B 10/12 comprising a MOSFET load element
• CPC Class Codes: H10B 10/125 the MOSFET being a thin film transistor [TFT]

Abstract

A circuit including an SRAM cell with a set of vertical nanowire transistor columns is provided. Each member of the set includes a vertical nanowire transistor and at least one member of the set is a vertical nanowire transistor column including two vertical nanowire transistors in series. The set can consist of four vertical nanowire transistor columns, a first column including two n-type vertical nanowire transistors, a second column including two n-type vertical nanowire transistors, a third column including one p-type vertical nanowire transistor and a fourth column including one p-type vertical nanowire transistor. EDA tools for such circuits are also provided.

Claims

1. A circuit, comprising:

an SRAM cell, the SRAM cell comprising a set of vertical nanowire transistor columns, each member of the set including a vertical nanowire transistor, and at least one member of the set being a vertical nanowire transistor column including two vertical nanowire transistors in series.

2. The circuit of claim 1, wherein the set consists of four vertical nanowire transistor columns, a first column including two n-type vertical nanowire transistors, a second column including two n-type vertical nanowire transistors, a third column including one p-type vertical nanowire transistor and a fourth column including one p-type vertical nanowire transistor.

3. The circuit of claim 2, wherein the four vertical nanowire transistor columns are arranged in layout at corners of a parallelogram.

4. The circuit of claim 2, wherein the four vertical nanowire transistor columns are arranged in layout at corners of a rectangle.

5. The circuit of claim 2, wherein the SRAM cell includes:

a first intra-cell connector (Q_R) connecting a current path terminal of the p-type vertical nanowire transistor (PU_R) in the fourth column to a current path terminal between the n-type vertical nanowire transistor (PD_R) in a first level and the n-type vertical nanowire transistor (PG_R) in a second level of the second column, and to gates of the n-type vertical nanowire transistor (PD_L) in first level of the first column and of the p-type vertical nanowire transistor (PU_L) in the third column; and

a second intra-cell connector (Q_L) connecting a current path terminal of the p-type vertical nanowire transistor (PU_L) in the third column to a current path terminal between the n-type vertical nanowire transistor (PD_L) in the first level and the n-type vertical nanowire transistor (PG_L) in the second level of the first column, and to gates of the n-type vertical nanowire transistor (PD_R) in first level of the second column and of the p-type vertical nanowire transistor (PU_R) in the fourth column.

6. The circuit of claim 5, wherein the four vertical nanowire transistor columns are arranged in layout at corners of a parallelogram, and the first intra-cell connector and the second intra-cell connector include respective first and second vias connecting the corresponding gates to the corresponding current path terminal, the first and second vias being disposed on opposing sides of the parallelogram.

7. The circuit of claim 5, wherein the four vertical nanowire transistor columns are arranged in layout at corners of a parallelogram, and the first intra-cell connector and the second intra-cell connector include respective first and second vias connecting the corresponding gates to the corresponding current path terminal, the first and second vias being disposed outside of the parallelogram.

8. The circuit of claim 5, wherein the four vertical nanowire transistor columns are arranged in layout at corners of a parallelogram, and the first intra-cell connector and the second intra-cell connector include respective first and second vias connecting the corresponding gates to the corresponding current path terminal, the first via being disposed inside of the parallelogram and the second via being disposed outside of the parallelogram.

9. The circuit of claim 1, wherein the SRAM cell includes a first conductor disposed beneath and contacting current path terminals of vertical nanowire transistors in a first subset of the vertical nanowire transistor columns, and a second conductor disposed beneath and contacting current path terminals of vertical nanowire transistors in a second subset of the vertical nanowire transistor columns.

10. The circuit of claim 2, wherein the SRAM cell includes a first conductor (V_SS) disposed beneath and contacting current path terminals of n-type vertical nanowire transistors in the first and second vertical nanowire transistor columns, and a second conductor (V_DD) disposed beneath and contacting current path terminals of p-type vertical nanowire transistors in the third and fourth vertical nanowire transistor columns.

11. The circuit of claim 2, where the SRAM cell includes:

a first bit line conductor (BL) disposed above and contacting a current path terminal of the n-type vertical nanowire transistor in the second level of the first vertical nanowire transistor column;

a second bit line conductor (BL/) disposed above and contacting a current path terminal of the n-type vertical nanowire transistor in the second level of the second vertical nanowire transistor column; and

a word line conductor (WL) connected to the gates of the n-type vertical nanowire transistors in the second level of the first and second vertical nanowire transistor columns.

12. A computer system adapted to process a computer implemented representation of a circuit design, comprising:

a processor and memory coupled to the processor, the memory storing instructions executable by the processor, including instructions to select cells from a cell library and/or to compile a memory layout using a selected cell;

the cell library including entries for a plurality of cells, entries in the cell library including specifications of particular cells in a computer executable language; and

at least one entry in the cell library, or the selected cell, comprising a specification of physical structures and timing parameters of an SRAM cell, the SRAM cell comprising a set of vertical nanowire transistor columns, each member of the set including a vertical nanowire transistor, and at least one member of the set being a vertical nanowire transistor column including two vertical nanowire transistors in series.

13. The computer system of claim 12, wherein the set consists of four vertical nanowire transistor columns, a first column including two n-type vertical nanowire transistors, a second column including two n-type vertical nanowire transistors, a third column including one p-type vertical nanowire transistor and a fourth column including one p-type vertical nanowire transistor.

14. The computer system of claim 13, wherein the four vertical nanowire transistor columns are arranged in layout at corners of a parallelogram.

15. The computer system of claim 13, wherein the four vertical nanowire transistor columns are arranged in layout at corners of a rectangle.

16. The computer system of claim 13, wherein the SRAM cell includes

a first intra-cell connector (Q_R) connecting a current path terminal of the p-type vertical nanowire transistor (PU_R) in the fourth column to a current path terminal between the n-type vertical nanowire transistor (PD_R) in a first level and the n-type vertical nanowire transistor (PG_R) in a second level of the second column, and to gates of the n-type vertical nanowire transistor (PD_L) in first level of the first column and of the p-type vertical nanowire transistor (PU_L) in the third column;

and

a second intra-cell connector (Q_L) connecting a current path terminal of the p-type vertical nanowire transistor (PU_L) in the third column to a current path terminal between the n-type vertical nanowire transistor (PD_L) in the first level and the n-type vertical nanowire transistor (PG_L) in the second level of the first column, and to gates of the n-type vertical nanowire transistor (PD_R) in the first level of the second column and of the p-type vertical nanowire transistor (PU_R) in the fourth column.

17. The computer system of claim 16, wherein the four vertical nanowire transistor columns are arranged in layout at corners of a parallelogram, and the first intra-cell connector and the second intra-cell connector include respective first and second vias connecting the corresponding gates to the corresponding current path terminal, the first and second vias being disposed on opposing sides of the parallelogram.

18. The computer system of claim 16, wherein the four vertical nanowire transistor columns are arranged in layout at corners of a parallelogram, and the first intra-cell connector and the second intra-cell connectors include respective first and second vias connecting the corresponding gates to the corresponding current path terminal, the first and second vias being disposed outside of the parallelogram.

19. The computer system of claim 16, wherein the four vertical nanowire transistor columns are arranged in layout at corners of a parallelogram, and the first intra-cell connector and the second intra-cell connector include respective first and second vias connecting the corresponding gates to the corresponding current path terminal, the first via being disposed inside of the parallelogram and the second via being disposed outside of the parallelogram.

20. The computer system of claim 12, wherein the SRAM cell includes a first conductor disposed beneath and contacting current path terminals of vertical nanowire transistors in a first subset of the vertical nanowire transistor columns, and a second conductor disposed beneath and contacting current path terminals of vertical nanowire transistors in a second subset of the vertical nanowire transistor columns.

21. The computer system of claim 13, wherein the SRAM cell includes a first conductor (V_SS) disposed beneath and contacting current path terminals of n-type vertical nanowire transistors in the first and second vertical nanowire transistor columns, and a second conductor (V_DD) disposed beneath and contacting current path terminals of p-type vertical nanowire transistors in the third and fourth vertical nanowire transistor columns.

22. The computer system of claim 13, where the SRAM cell includes:

a first bit line conductor (BL) disposed above and contacting a current path terminal of the n-type vertical nanowire transistor in the second level of the first vertical nanowire transistor column;

a second bit line conductor (BL/) disposed above and contacting a current path terminal of the n-type vertical nanowire transistor in the second level of the second vertical nanowire transistor column; and

a word line conductor (WL) connected to the gates of the n-type vertical nanowire transistors in the second level of the first and second vertical nanowire transistor columns.

23. The computer system of claim 12, wherein the instructions further include logic to utilize the specification in said at least one entry to determine a physical placement of the cell.

24. A computer program product, comprising:

a memory device having stored thereon a machine readable specification of a cell, the specification of the cell including computer readable parameters specifying structural features of a physical implementation of a circuit, the specification being executable by a computer running a placement process to control physical placement of the circuit with other circuits or components or for use by a memory compiler to compile a memory array using the cell, the circuit including;

an SRAM cell, the SRAM cell comprising a set of vertical nanowire transistor columns, each member of the set including a vertical nanowire transistor, and at least one member of the set being a vertical nanowire transistor column including two vertical nanowire transistors in series.

25. The computer program product of claim 24, wherein the set consists of four vertical nanowire transistor columns, a first column including two n-type vertical nanowire transistors, a second column including two n-type vertical nanowire transistors, a third column including one p-type vertical nanowire transistor and a fourth column including one p-type vertical nanowire transistor.

26. The computer program product of claim 25, wherein the four vertical nanowire transistor columns are arranged in layout at corners of a parallelogram.

27. The computer program product of claim 25, wherein the four vertical nanowire transistor columns are arranged in layout at corners of a rectangle.

28. The computer program product of claim 25, wherein the SRAM cell includes:

a first intra-cell connector (Q_R) connecting a current path terminal of the p-type vertical nanowire transistor (PU_R) in the fourth column to a current path terminal between the n-type vertical nanowire transistor (PD_R) in a first level and the n-type vertical nanowire transistor (PG_R) in a second level of the second column, and to gates of the n-type vertical nanowire transistor (PD_L) in the first level of the first column and of the p-type vertical nanowire transistor (PU_L) in the third column; and

a second intra-cell connector (Q_L) connecting a current path terminal of the p-type vertical nanowire transistor (PU_L) in the third column to a current path terminal between the n-type vertical nanowire transistor (PD_L) in the first level and the n-type vertical nanowire transistor (PG_L) in the second level of the first column, and to gates of the n-type vertical nanowire transistor (PD_R) in the first level of the second column and of the p-type vertical nanowire transistor (PU_R) in the fourth column.

29. The computer program product of claim 28, wherein the four vertical nanowire transistor columns are arranged in layout at corners of a parallelogram, and the first intra-cell connector and the second intra-cell connector include respective first and second vias connecting the corresponding gates to the corresponding current path terminal, the first and second vias being disposed on opposing sides of the parallelogram.

30. The computer program product of claim 28, wherein the four vertical nanowire transistor columns are arranged in layout at corners of a parallelogram, and the first intra-cell connector and the second intra-cell connector include respective first and second vias connecting the corresponding gates to the corresponding current path terminal, the first and second vias being disposed outside of the parallelogram.

31. The computer program product of claim 28, wherein the four vertical nanowire transistor columns are arranged in layout at corners of a parallelogram, and the first intra-cell connector and the second intra-cell connector include respective first and second vias connecting the corresponding gates to the corresponding current path terminal, the first via being disposed inside of the parallelogram and the second via being disposed outside of the parallelogram.

32. The computer program product of claim 24, wherein the SRAM cell includes a first conductor disposed beneath and contacting current path terminals of vertical nanowire transistors in a first subset of the vertical nanowire transistor columns, and a second conductor disposed beneath and contacting current path terminals of vertical nanowire transistors in a second subset of the vertical nanowire transistor columns.

33. The computer program product of claim 25, wherein the SRAM cell includes a first conductor (V_SS) disposed beneath and contacting current path terminals of n-type vertical nanowire transistors in the first and second vertical nanowire transistor columns, and a second conductor (V_DD) disposed beneath and contacting current path terminals of p-type vertical nanowire transistors in the third and fourth vertical nanowire transistor columns.

34. The computer program product of claim 25, where the SRAM cell includes:

a first bit line conductor (BL) disposed above and contacting a current path terminal of the n-type vertical nanowire transistor in the second level of the first vertical nanowire transistor column;

a second bit line conductor (BL/) disposed above and contacting a current path terminal of the n-type vertical nanowire transistor in the second level of the second vertical nanowire transistor column; and

a word line conductor (WL) connected to the gates of the n-type vertical nanowire transistors in the second level of the first and second vertical nanowire transistor columns.

35. The computer program product of claim 24, further including logic to utilize the specification of the cell to determine a physical placement of the circuit.