Methods and devices to improve switching time by bypassing gate resistor

• US 10,396,772 B2
• Filed: 12/12/2016
• Issued: 08/27/2019
• Est. Priority Date: 12/12/2016
• Status: Active Grant

• Current Assignee: pSemi Corporation (Murata Manufacturing Co Limited)
• Original Assignee: pSemi Corporation (Murata Manufacturing Co Limited)
• Inventors: Shanjani, Payman, Shapiro, Eric S.
• Primary Examiner(s): Hiltunen, Thomas J.
• Application Number:
  US15/376,471
• Publication Number:
  US 20180167062A1
• Time in Patent Office: 988 Days
• CPC Class Codes: H03K 17/04123 in field-effect transistor switches

Abstract

Implementing a series gate resistor in a switching circuit results in several performance improvements. Few examples are better insertion loss, lower breakdown voltage requirements and a lower frequency corner. These benefits come at the expense of a slower switching time. Methods and devices offering solutions to this problem are described. Using a concept of bypassing the series gate resistor during transition time, a fast switching time can be achieved while the above-mentioned performance improvements are maintained.

Claims

1. A switching circuit comprising:

a first node;

a second node;

a first terminal;

a second terminal;

a third terminal;

a fourth terminal;

a main FET switch stack;

a bypass FET switch stack, and

wherein;

the main FET switch stack comprises;

a series arrangement of a plurality of main FET switches coupled between the first node and the second node, and

a plurality of main gate resistors, the plurality of the main gate resistors connecting the second terminal to corresponding gates of the plurality of the main FET switches;

the bypass FET switch stack comprises;

a series arrangement of a plurality of first bypass FET switches;

a series arrangement of a plurality of second bypass FET switches;

a plurality of first bypass gate resistors;

the plurality of the first bypass gate resistors connecting corresponding gates of the plurality of the first bypass FET switches to the third terminal;

a plurality of second bypass gate resistors;

the plurality of the second bypass gate resistors connecting corresponding gates of the plurality of the second bypass FET switches to the fourth terminal, and

a plurality of drain-source resistances, the plurality of the drain-source resistors being coupled across the corresponding drains and sources of the plurality of the first and the second bypass FET switches;

wherein;

drains and sources of the first bypass FET switches are connected to corresponding drains and sources of the second bypass FET switches respectively;

the drains of the bypass FET switches closest to the first terminal and farthest from the second terminal are connected to the first terminal;

the sources of the bypass FET switches closest to the second terminal and farthest from the first terminal are connected to the second terminal;

wherein;

a first supply voltage applied to the first terminal is configured to transition the plurality of the main FET switches from an OFF to an ON state and vice versa;

a second supply voltage applied to the third terminal is configured to open the plurality of the first bypass FET switches when the plurality of the main FET switches are in the OFF or the ON state and to close the plurality of the first bypass FET switches when the plurality of the main FET switches is transitioning from the OFF to the ON state, and

a third supply voltage applied to the fourth terminal is configured to open the plurality of the second bypass FET switches when the plurality of the main FET switches are in the OFF or the ON state and to close the plurality of the second bypass FET switches when the plurality of the main FET switches is transitioning from the ON to the OFF state.

2. The switching circuit of claim 1, wherein the plurality of first bypass switches comprises at least one n-channel FET and the plurality of the second bypass switches comprises at least one p-channel FET.

3. The switching circuit of claim 2, wherein the at least one n-channel FET and the at least one p-channel FET are NMOS FET and PMOS FET respectively.

4. The switching circuit of claim 1, wherein:

the ratio of a size of each of the plurality of the first bypass switches to a size of each of the plurality of main FET switches is less than 1/100, and/or

the ratio of a size of each of the plurality of the second bypass switches to a size of each of the plurality of main FET switches is less than 1/100.