Semiconductor device and method of manufacturing the semiconductor device

• US 10,446,444 B2
• Filed: 11/21/2018
• Issued: 10/15/2019
• Est. Priority Date: 12/20/2016
• Status: Active Grant

• Current Assignee: SK Hynix Inc.
• Original Assignee: SK Hynix Inc.
• Inventors: Kim, Jong Su
• Primary Examiner(s): Slutsker, Julia
• Application Number:
  US16/198,546
• Publication Number:
  US 20190088546A1
• Time in Patent Office: 328 Days
• CPC Class Codes: H01L 21/76834 formation of thin insulating films on the sidewalls or on top of conductors H01L21/76831 takes precedence
• CPC Class Codes: H01L 21/76885 By forming conductive members before deposition of protective insulating material, e.g. pillars, studs
• CPC Class Codes: H01L 21/76898 formed through a semiconductor substrate
• CPC Class Codes: H01L 23/5222 Capacitive arrangements or effects of, or between wiring layers other capacitive arrangements H01L23/642
• CPC Class Codes: H01L 23/5223 Capacitor integral with wiring layers
• CPC Class Codes: H01L 23/5226 Via connections in a multilevel interconnection structure
• CPC Class Codes: H01L 23/5283 Cross-sectional geometry
• CPC Class Codes: H01L 23/5286 Arrangements of power or ground buses
• CPC Class Codes: H01L 23/53204 Conductive materials
• CPC Class Codes: H01L 23/53295 Stacked insulating layers
• CPC Class Codes: H01L 23/5386 Geometry or layout of the interconnection structure

Abstract

An interconnection structure of the semiconductor integrated circuit device may be provided. The interconnection structure may include a first conductive pattern, a second conductive pattern, a dielectric layer and a contact part. The first conductive pattern may have a first width and a first length. The second conductive pattern may be formed over the first conductive pattern. The second conductive pattern may have a second width and a second length. The dielectric layer may be interposed between the first conductive pattern and the second conductive pattern. The contact part may be configured to simultaneously make contact with the first conductive pattern and the second conductive pattern.

Claims

1. A method of manufacturing an interconnection structure of a semiconductor integrated circuit device, the method comprising:

forming a first conductive layer on a semiconductor substrate;

treating a surface of the first conductive layer to form a dielectric layer;

forming a second conductive layer on the dielectric layer;

patterning the second conductive layer and the dielectric layer to form a second conductive pattern;

patterning the first conductive layer to form a first conductive pattern having a length longer than that of the second conductive pattern; and

forming a contact part to electrically connect the first conductive pattern and the second conductive pattern,

wherein the contact part is formed to simultaneously make contact with an upper surface of the first conductive pattern and an edge portion of the second conductive pattern.

2. The method of claim 1, wherein forming the dielectric layer comprises at least one of performing a nitrogen treatment process or an argon treatment process on the surface of the first conductive layer.

3. The method of claim 1, wherein the first conductive pattern has a width substantially the same as that of the second conductive pattern.

4. The method of claim 1, wherein forming the contact part comprises;

forming an insulating interlayer on the semiconductor substrate after forming the first conductive pattern;

etching the insulating interlayer to form a contact hole configured to simultaneously expose the first and second conductive patterns; and

filling the contact hole with a conductive material.

9. The method of claim 4, wherein the contact hole exposes the one end of the second conductive pattern and the upper surface of the first conductive pattern exposed by the second conductive pattern.

5. A method of manufacturing an interconnection structure of a semiconductor integrated circuit device, the method comprising:

forming a first conductive layer on a semiconductor substrate;

treating a surface of the first conductive layer to form a dielectric layer;

forming a second conductive layer on the dielectric layer;

patterning the second conductive layer and the dielectric layer to form a second conductive pattern;

forming a spacer on a sidewall of the second conductive pattern;

etching the first conductive layer using the spacer and the second conductive pattern as an etch mask to form a first conductive pattern; and

forming a contact part to connect the first conductive pattern and the second conductive pattern,

wherein the contact part is formed to simultaneously make contact with an upper surface of the first conductive pattern exposed by the second conductive pattern and one sidewall of the second conductive pattern.

6. The method of claim 5, wherein forming the dielectric layer comprises performing a nitrogen treatment process or an argon treatment process on the surface of the first conductive layer.

7. The method of claim 5, wherein forming the contact part comprises;

forming an insulating interlayer on the semiconductor substrate after forming the first conductive pattern;

etching the insulating interlayer and the spacer to form a contact hole configured to simultaneously expose the first and second conductive patterns; and

filling the contact hole with a conductive material.

8. The method of claim 7, wherein the contact hole exposes the one end of the second conductive pattern and the upper surface of the first conductive pattern exposed by the second conductive pattern.

10. A method of manufacturing an interconnection structure of a semiconductor integrated circuit device, the method comprising:

forming a first conductive layer on a semiconductor substrate;

treating a surface of the first conductive layer to form a dielectric layer;

forming a second conductive layer on the dielectric layer;

patterning the second conductive layer and the dielectric layer to form a plurality of second conductive patterns;

patterning the first conductive layer to form a plurality of first conductive patterns, wherein the plurality of second conductive patterns are respectively disposed over the plurality of first conductive patterns, and at least one end of each first conductive pattern is exposed by each second conductive pattern; and

forming a plurality of contact parts to electrically connect the plurality of first conductive patterns and the plurality of second conductive patterns, thereby forming a plurality of interconnections,

wherein each contact part is formed to simultaneously make contact with an exposed surface of the each first conductive pattern and one end of the each second conductive pattern.

11. The method of claim 10, wherein the each first conductive pattern is formed to have a length longer than that of the each second conductive pattern, thereby exposing an upper surface and a sidewall of the one end of the first conductive pattern.

12. The method of claim 11, wherein the each first conductive pattern is formed to have a width substantially the same as that of the second conductive pattern.

13. The method of claim 10, wherein the each second conductive pattern is formed to have a width narrower than the each first conductive pattern, thereby exposing an upper surface and at least one sidewalls of the first conductive pattern.

14. The method of claim 13, wherein the patterning the first conductive layer, comprises:

forming a spacer on a sidewall of the second conductive pattern; and

etching the first conductive layer using the spacer and the second conductive pattern as an etch mask to form the first conductive pattern.

15. The method of claim 10, wherein the forming the contact parts comprises;

forming an insulating interlayer on the semiconductor substrate after forming the first conductive patterns;

etching the insulating interlayer to form contact holes configured to simultaneously expose the first and second conductive patterns; and

filling the contact holes with a conductive material.

16. The method of claim 10, further comprising:

forming an insulating interlayer between the plurality of the interconnections,

wherein capacitors are generated between the plurality of interconnections, respectively.