Methods for reducing scratch defects in chemical mechanical planarization

• US 10,522,365 B2
• Filed: 06/14/2016
• Issued: 12/31/2019
• Est. Priority Date: 01/27/2016
• Status: Active Grant

• Current Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Original Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Inventors: Pan, Wan-Chun, Hong, William Weilun, Chen, Ying-Tsung
• Primary Examiner(s): Ahmadi, Mohsen
• Assistant Examiner(s): Bauman, Scott E
• Application Number:
  US15/182,291
• Publication Number:
  US 20170213743A1
• Time in Patent Office: 1,295 Days
• Field of Search: 438424
• CPC Class Codes: H01L 21/02164 the material being a silicon oxide, e.g. SiO2
• CPC Class Codes: H01L 21/02205 the layer being characterised by the precursor material for deposition
• CPC Class Codes: H01L 21/02323 introduction of oxygen
• CPC Class Codes: H01L 21/02337 treatment by exposure to a gas or vapour
• CPC Class Codes: H01L 21/02343 treatment by exposure to a liquid
• CPC Class Codes: H01L 21/3105 After-treatment
• CPC Class Codes: H01L 21/31051 Planarisation of the insulating layers H01L21/31058 takes precedence
• CPC Class Codes: H01L 21/31053 involving a dielectric removal step
• CPC Class Codes: H01L 21/76224 using trench refilling with dielectric materials trench filling with polycristalline silicon H01L21/763; together with vertical isolation, e.g. trench refilling in a SOI substrate H01L21/76264
• CPC Class Codes: H01L 21/823431 with a particular manufacturing method of transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 21/823481 isolation region manufacturing related aspects, e.g. to avoid interaction of isolation region with adjacent structure
• CPC Class Codes: H01L 21/845 including field-effect transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET

Abstract

Disclosed is a method of forming a semiconductor device. The method includes providing a precursor having a substrate and protrusions over the substrate. The protrusions are interposed by trenches. The method further includes depositing a first dielectric layer over the protrusions and filling the trenches. The first dielectric layer has a first hardness. The method further includes treating the first dielectric layer with an oxidizer. The method further includes performing a chemical mechanical planarization (CMP) process to the first dielectric layer.

Claims

1. A method of forming a semiconductor device, the method comprising:

providing a precursor having a substrate and protrusions over the substrate, the protrusions being interposed by trenches;

depositing a first dielectric layer over the protrusions and filling the trenches, the first dielectric layer having a first hardness;

treating the first dielectric layer with an oxidizer, resulting in a treated portion of the first dielectric layer;

after the treating of the first dielectric layer, depositing a second dielectric layer over the treated portion of the first dielectric layer, wherein the second dielectric layer has a second hardness higher than the first hardness; and

performing a chemical mechanical planarization (CMP) process to both the first dielectric layer and the second dielectric layer to completely remove the second dielectric layer and to partially remove the treated portion of the first dielectric layer,

wherein the treating of the first dielectric layer is performed at a temperature ranging from 15°

C. to 90°

C. and the oxidizer is dilute hydrofluoric acid (DHF) and a concentration of hydrofluoric acid in the oxidizer ranges from 0.005% to 0.1%.

2. The method of claim 1, wherein the treated portion of the first dielectric layer extends below a top surface of the protrusions.

3. The method of claim 1, wherein the treating of the first dielectric layer is performed at room temperature.

4. The method of claim 1, wherein the oxidizer is aqueous.

5. The method of claim 1, after the treating the first dielectric layer with an oxidizer, further comprising treating the first dielectric layer with deionized water (DIW).

6. The method of claim 1, wherein an aspect ratio between a height and a width of the trenches is greater than 12.

7. The method of claim 1, wherein the first and second dielectric layers include silicon and oxygen.

8. The method of claim 1, wherein the protrusions include semiconductor fins.

9. The method of claim 1, wherein the protrusions include gate structures.

10. A method of forming a semiconductor device, the method comprising:

providing a precursor having a substrate and fins over the substrate, the fins being interposed by trenches;

depositing a first dielectric layer over the fins and filling the trenches, the first dielectric layer containing silicon and oxygen and having a first hardness;

treating the first dielectric layer with an aqueous oxidizer, resulting in a treated portion of the first dielectric layer above an untreated portion of the first dielectric layer, the treated portion of the first dielectric layer having a second hardness greater than the first hardness;

depositing a second dielectric layer over the treated portion of the first dielectric layer, wherein the second dielectric layer contains silicon and oxygen and has a third hardness higher than the first hardness; and

performing a chemical mechanical planarization (CMP) process to completely remove the second dielectric layer and partially remove the treated portion of the first dielectric layer, wherein the treating of the first dielectric layer is performed at a temperature ranging from 15 degrees Celsius (°

C.) to 90°

C.

11. The method of claim 10, wherein the aqueous oxidizer is deionized water (DIW).

12. The method of claim 10, wherein the aqueous oxidizer is dilute hydrofluoric acid (DHF).

13. The method of claim 10, wherein a concentration of hydrofluoric acid in the aqueous oxidizer ranges from 0.005% to 0.1%.

14. The method of claim 10, wherein the treating the first dielectric layer with an aqueous oxidizer includes a first treating process with DIW and a second treating process with DHF.

15. A method of forming a semiconductor device, the method comprising:

providing a precursor having a substrate and protrusions over the substrate, the protrusions being interposed by trenches;

depositing a first dielectric layer over the protrusions and filling the trenches, the first dielectric layer containing silicon and oxygen;

treating the first dielectric layer with an aqueous oxidizer at a temperature lower than 100 degrees Celsius (°

C.), resulting in a treated portion of the first dielectric layer;

depositing a second dielectric layer over the treated portion, wherein the second dielectric layer contains silicon and oxygen; and

performing a chemical mechanical planarization (CMP) process to completely remove the second dielectric layer and partially remove the treated portion of the first dielectric layer.

16. The method of claim 15, wherein the aqueous oxidizer is one of:

deionized water (DIW) and dilute hydrofluoric acid (DHF).

17. The method of claim 15, wherein the first dielectric layer has a first hardness before the treating of the first dielectric layer, the treated portion has a second hardness greater than the first hardness, and the second dielectric layer has a third hardness higher than the first hardness.

18. The method of claim 15, wherein the treating the first dielectric layer with an aqueous oxidizer includes a first treating process with DIW and a second treating process with DHF.

19. The method of claim 18, wherein a concentration of hydrofluoric acid in the DHF ranges from 0.005% to 0.1%.

20. The method of claim 18, prior to the treating the first dielectric layer with an aqueous oxidizer, further comprising an annealing process at a temperature ranging between 300°

C. to 1200°

C.