Methods for Reducing Scratch Defects in Chemical Mechanical Planarization

• US 20170213743A1
• Filed: 06/14/2016
• Published: 07/27/2017
• Est. Priority Date: 01/27/2016
• Status: Active Grant

• Current Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Original Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Inventors: Pan, Wan-Chun, Hong, William Weilun, Chen, Ying-Tsung
• Granted Patent: US 10,522,365 B2
• Time in Patent Office: Days
• CPC Class Codes: H01L 21/02164 the material being a silicon oxide, e.g. SiO2
• CPC Class Codes: H01L 21/02205 the layer being characterised by the precursor material for deposition
• CPC Class Codes: H01L 21/02323 introduction of oxygen
• CPC Class Codes: H01L 21/02337 treatment by exposure to a gas or vapour
• CPC Class Codes: H01L 21/02343 treatment by exposure to a liquid
• CPC Class Codes: H01L 21/3105 After-treatment
• CPC Class Codes: H01L 21/31051 Planarisation of the insulating layers H01L21/31058 takes precedence
• CPC Class Codes: H01L 21/31053 involving a dielectric removal step
• CPC Class Codes: H01L 21/76224 using trench refilling with dielectric materials trench filling with polycristalline silicon H01L21/763; together with vertical isolation, e.g. trench refilling in a SOI substrate H01L21/76264
• CPC Class Codes: H01L 21/823431 with a particular manufacturing method of transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 21/823481 isolation region manufacturing related aspects, e.g. to avoid interaction of isolation region with adjacent structure
• CPC Class Codes: H01L 21/845 including field-effect transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET

Abstract

Disclosed is a method of forming a semiconductor device. The method includes providing a precursor having a substrate and protrusions over the substrate. The protrusions are interposed by trenches. The method further includes depositing a first dielectric layer over the protrusions and filling the trenches. The first dielectric layer has a first hardness. The method further includes treating the first dielectric layer with an oxidizer. The method further includes performing a chemical mechanical planarization (CMP) process to the first dielectric layer.

Claims

1. A method of forming a semiconductor device, the method comprising:

providing a precursor having a substrate and protrusions over the substrate, the protrusions being interposed by trenches;

depositing a first dielectric layer over the protrusions and filling the trenches, the first dielectric layer having a first hardness;

treating the first dielectric layer with an oxidizer; and

performing a chemical mechanical planarization (CMP) process to the first dielectric layer.

2. The method of claim 1, wherein a treated portion of the first dielectric layer extends below a top surface of the protrusions.

3. The method of claim 1, wherein the treating of the first dielectric layer is performed at a temperature below 100 degrees Celsius (°

C.).

4. The method of claim 1, wherein the oxidizer is aqueous.

5. The method of claim 4, wherein the treating of the first dielectric layer is performed at a temperature ranging from 15°

C. to 90°

C.

6. The method of claim 5, wherein the oxidizer is deionized water (DIW).

7. The method of claim 5, wherein the oxidizer is dilute hydrofluoric acid (DHF).

8. The method of claim 7, wherein a concentration of hydrofluoric acid in the oxidizer ranges from 0.005% to 0.1%.

9. The method of claim 1, wherein an aspect ratio between a height and a width of the trenches is greater than 12.

10. The method of claim 1, further comprising, after the treating of the first dielectric layer and before the performing of the CMP process:

depositing a second dielectric layer over the first dielectric layer, wherein the second dielectric layer has a second hardness higher than the first hardness, wherein the CMP process is also performed to the second dielectric layer.

11. The method of claim 10, wherein the first and second dielectric layers include silicon oxide.

12. The method of claim 1, wherein the protrusions include semiconductor fins.

13. The method of claim 1, wherein the protrusions include gate structures.

14. A method of forming a semiconductor device, the method comprising:

providing a precursor having a substrate and fins over the substrate, the fins being interposed by trenches;

depositing a first silicon oxide layer over the fins and filling the trenches, the first silicon oxide layer having a first hardness;

treating the first silicon oxide layer with an aqueous oxidizer, resulting in a treated portion of the first silicon oxide layer above an untreated portion of the first silicon oxide layer, the treated portion of the first silicon oxide layer having a second hardness greater than the first hardness;

depositing a second silicon oxide layer over the treated portion of the first silicon oxide layer, wherein the second silicon oxide layer has a third hardness higher than the first hardness; and

performing a chemical mechanical planarization (CMP) process to the second and first silicon oxide layers.

15. The method of claim 14, wherein the oxidizer is deionized water (DIW).

16. The method of claim 14, wherein the oxidizer is dilute hydrofluoric acid (DHF).

17. The method of claim 14, wherein a concentration of hydrofluoric acid in the oxidizer ranges from 0.005% to 0.1%.

18. The method of claim 14, wherein the treating of the first silicon oxide layer is performed at a temperature ranging from 15 degrees Celsius (°

C.) to 90°

C.

19. A method of forming a semiconductor device, the method comprising:

providing a precursor having a substrate and protrusions over the substrate, the protrusions being interposed by trenches;

depositing a first silicon oxide layer over the protrusions and filling the trenches, the first silicon oxide layer having a first hardness;

treating the first silicon oxide layer with an aqueous oxidizer at a temperature lower than 100 degrees Celsius (°

C.), resulting in a treated portion of the first silicon oxide layer, wherein the treated portion has a second hardness greater than the first hardness;

depositing a second silicon oxide layer over the treated portion, wherein the second silicon oxide layer has a third hardness higher than the first hardness; and

performing a chemical mechanical planarization (CMP) process to the second and first silicon oxide layers.

20. The method of claim 19, wherein the oxidizer is one of:

deionized water (DIW) and dilute hydrofluoric acid (DHF).