Processor power management

• US 10,579,121 B2
• Filed: 04/01/2017
• Issued: 03/03/2020
• Est. Priority Date: 04/01/2017
• Status: Active Grant

• Current Assignee: Intel Corporation
• Original Assignee: Intel Corporation
• Inventors: Koker, Altug, Appu, Abhishek R., Veernapu, Kiran C., Ray, Joydeep, Vembu, Balaji, Surti, Prasoonkumar, Sinha, Kamal, Hoekstra, Eric J., Fu, Wenyin, Kaburlasos, Nikos, Borole, Bhushan M., Schluessler, Travis T., Shah, Ankur N., Kennedy, Jonathan
• Primary Examiner(s): Pardo, Thuy N
• Application Number:
  US15/477,029
• Publication Number:
  US 20180284868A1
• Time in Patent Office: 1,067 Days
• Field of Search: 345 47, 345501, 345589, 345633, 345156, 345173, 345502, 345506, 726 22, 705 3, 709226, 713320
• CPC Class Codes: G06F 1/3203 Power management, i.e. event-based initiation of a power-saving mode
• CPC Class Codes: G06F 1/3209 Monitoring remote activity, e.g. over telephone lines or network connections
• CPC Class Codes: G06F 1/3212 Monitoring battery levels, e.g. power saving mode being initiated when battery voltage goes below a certain level
• CPC Class Codes: G06F 1/3218 of display devices
• CPC Class Codes: G06F 1/3231 Monitoring the presence, absence or movement of users
• CPC Class Codes: G06F 1/324 by lowering clock frequency
• CPC Class Codes: G06F 11/0781 Error filtering or prioritizing based on a policy defined by the user or on a policy defined by a hardware/software module, e.g. according to a severity level
• CPC Class Codes: G06F 11/3062 where the monitored property is the power consumption power management in a computing system G06F1/3203
• CPC Class Codes: G06F 3/01 Input arrangements or combined input and output arrangements for interaction between user and computer G06F3/16 takes precedence
• CPC Class Codes: H04M 1/72448 with means for adapting the functionality of the device according to specific conditions
• CPC Class Codes: H04W 52/0258 controlling an operation mode according to history or models of usage information, e.g. activity schedule or time of day
• CPC Class Codes: Y02D 10/00 Energy efficient computing, e.g. low power processors, power management or thermal management
• CPC Class Codes: Y02D 30/70 in wireless communication networks

Abstract

Methods and apparatus relating to techniques for avoiding cache lookup for cold cache. In an example, an apparatus comprises logic, at least partially comprising hardware logic, to collect user information for a user of a data processing device, generate a user profile for the user of the data processing device from the user information, and set a power profile a processor in the data processing device using the user profile. Other embodiments are also disclosed and claimed.

Claims

1. A graphics multiprocessor comprising:

an instruction cache to receive a stream of instructions;

an instruction unit to dispatch instructions in the stream of instructions for execution;

a general-purpose graphics processing compute block comprising a plurality of graphics processing cores;

a shared memory communicatively coupled to the plurality of graphics processing cores; and

a processor to;

collect user information for a user of the graphics multiprocessor and one or more performance parameters of the graphics multiprocessor, the performance parameters comprising at least one of a silicon stepping parameter, a memory parameter, and a cooling capacity parameter;

generate a user profile for the user of the graphics multiprocessor from the user information;

generate a training set based on the user information and the one or more performance parameters;

train a neural network to obtain at least one of a sustained rate at a predetermined level of temperature or power or a maximum frame rate or;

select a state point that defines a hardware programming state of one or more registers and one or more shader compilers in the graphics multiprocessor to control performance of the graphics multiprocessor;

generate a hardware register setting hash based on a combination of the hardware programming state and the one or more shader compilers; and

set a power level for one or more of the plurality of graphics processing cores using the hardware register setting hash and the user profile.

2. The graphics multiprocessor of claim 1, the processor to:

collect at least one of a graphics workload level consumed by the user or a processor power consumption consumed by the user.

3. The graphics multiprocessor of claim 1, the processor to:

collect at least one of a user'"'"'s approximate age, eyesight level, a list of applications routinely used by the user, or a screen brightness level.

4. The graphics multiprocessor of claim 1, the processor to:

recall a user profile from memory when a user logs into the processor; and

update the user profile updated during the user'"'"'s session.

5. The graphics multiprocessor of claim 1, the processor to:

categorize the user into one of a plurality of power consumption categories based on the user profile.

6. The graphics multiprocessor of claim 5, the processor to:

limit a frequency push of one or more of the plurality of graphics processing cores based at least in part on the user profile.

7. The graphics multiprocessor of claim 5, the processor to:

drive one or more of the plurality of graphics processing cores directly into a high-performance mode based at least in part on the user profile.

8. An electronic device, comprising:

a display; and

a graphics multiprocessor comprising;

a general-purpose graphics processing compute block having one or more graphics processing cores;

an instruction cache to receive a stream of instructions;

an instruction unit to dispatch instructions in the stream of instructions for execution;

a general-purpose graphics processing compute block comprising a plurality of graphics processing cores;

a shared memory communicatively coupled to the plurality of graphics processing cores; and

a processor to;

collect user information for a user of the graphics multiprocessor and one or more performance parameters of the graphics multiprocessor, the performance parameters comprising at least one of a silicon stepping parameter, a memory parameter, and a cooling capacity parameter;

generate a user profile for the user of the graphics multiprocessor from the user information;

generate a training set based on the user information and the one or more performance parameters;

train a neural network to obtain at least one of a sustained rate at a predetermined level of temperature or power or a maximum frame rate or;

select a state point that defines a hardware programming state of one or more registers and one or more shader compilers in the graphics multiprocessor to control performance of the graphics multiprocessor;

generate a hardware register setting hash based on a combination of the hardware programming state and the one or more shader compilers.

9. The electronic device of claim 8, the processor to:

collect at least one of a graphics workload level consumed by the user or a processor power consumption consumed by the user.

10. The electronic device of claim 8, the processor to:

collect at least one of a user'"'"'s approximate age, eyesight level, a list of applications routinely used by the user, or a screen brightness level.

11. The electronic device of claim 8, the processor to:

recall a user profile from memory when a user logs into the processor; and

update the user profile updated during the user'"'"'s session.

12. The electronic device of claim 8, the processor to:

categorize the user into one of a plurality of power consumption categories based on the user profile.

13. The electronic device of claim 12, the processor to:

limit a frequency push of one or more of the plurality of graphics processing cores based at least in part on the user profile.

14. The electronic device of claim 12, the processor to:

drive one or more of the plurality of graphics processing cores directly into a high-performance mode based at least in part on the user profile.