MEMS package with roughend interface

• US 10,710,872 B2
• Filed: 12/06/2017
• Issued: 07/14/2020
• Est. Priority Date: 12/13/2016
• Status: Active Grant

• Current Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Original Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Inventors: Chen, Yu-Jui, Wang, I-Shi, Lee, Ren-Dou, Liu, Jen-Hao
• Primary Examiner(s): Chin, Edward
• Application Number:
  US15/833,072
• Publication Number:
  US 20180162720A1
• Time in Patent Office: 951 Days
• CPC Class Codes: B81B 7/007 Interconnections between the MEMS and external electrical signals
• CPC Class Codes: B81B 7/0077 Other packages not provided for in groups B81B7/0035 - B81B7/0074
• CPC Class Codes: B81B 7/02 containing distinct electrical or optical devices of particular relevance for their function, e.g. microelectro-mechanical systems [MEMS] B81B7/04 takes precedence
• CPC Class Codes: B81C 1/00238 Joining a substrate with an electronic processing unit and a substrate with a micromechanical structure
• CPC Class Codes: B81C 1/00269 Bonding of solid lids or wafers to the substrate
• CPC Class Codes: B81C 2203/019 characterised by the material or arrangement of seals between parts
• CPC Class Codes: B81C 2203/054 using structural alignment aids, e.g. spacers, interposers, male/female parts, rods or balls
• CPC Class Codes: B81C 2203/0735 Post-CMOS, i.e. forming the micromechanical structure after the CMOS circuit
• CPC Class Codes: B81C 2203/075 the electronic processing unit being integrated into an element of the micromechanical structure
• CPC Class Codes: B81C 3/005 Passive alignment, i.e. without a detection of the position of the elements or using only structural arrangements or thermodynamic forces
• CPC Class Codes: B81C 3/008 Aspects related to assembling from individually processed components, not covered by groups B81C3/001 - B81C3/002

Abstract

A method includes: providing a first substrate on which a plurality of first semiconductor devices is formed; providing a second substrate on which a plurality of second semiconductor devices is formed; and coupling the first and second substrates by contacting respective dummy pads of the first and second substrates, wherein at least one of the dummy pads of the first and second substrates comprises plural peaks and valleys.

Claims

1. A method, comprising:

providing a first substrate on which a plurality of first semiconductor devices is formed;

providing a second substrate on which a plurality of second semiconductor devices is formed;

roughening a top surface of a first dummy pad extending outwardly from the first substrate, wherein the first dummy pad is formed as a ring-shape configuration that surrounds the plurality of first semiconductor devices;

roughening a top surface of a second dummy pad extending outwardly from the second substrate, wherein the second dummy pad is formed as a ring-shape configuration that surrounds the plurality of second semiconductor devices;

providing a first bonding pad extending outwardly from the first substrate, the first bonding pad being surrounded by the first dummy pad; and

providing a second bonding pad extending outwardly from the second substrate, the second bonding pad being surrounded by the second dummy pad, wherein the first and second bonding pads are located so as to be bonded with each other when the first and second substrates are coupled to one another;

coupling the first and second substrates by contacting the roughened top surfaces of the first and second dummy pads with each other so as to limit a lateral shift between the first and second substrates, wherein each of the top surfaces of the first and second dummy pads of the first and second substrates comprises plural peaks and valleys; and

providing a metal plate around an edge of a top surface of the second substrate so as to prevent lateral shifting between the first and second substrates after they are coupled to one another.

2. The method of claim 1, wherein the first semiconductor device comprises a micro-electro-mechanical system (MEMS) device.

3. The method of claim 1, wherein the second semiconductor device comprises a complementary metal-oxide-semiconductor (CMOS) circuit.

4. The method of claim 1, wherein before coupling the first and second substrates, the method further comprises:

flipping the second substrate and aligning the first semiconductor device with the second semiconductor device.

5. The method of claim 1, wherein the first dummy pad of the first substrate is disposed in a non-active region on the first substrate where the plurality of first semiconductor devices are absent.

6. The method of claim 1, wherein the second dummy pad of the second substrate is disposed in a non-active region on the second substrate where the plurality of second semiconductor devices are absent.

7. The method of claim 1, wherein the coupling the first and second substrates further comprises:

bonding the first and second bonding pads to each other under an elevated temperature.

8. The method of claim 7, further comprising:

forming a eutectic layer on a top surface of the first bonding pad of the first substrate before the bonding process.

9. A method, comprising:

providing a first substrate on which a plurality of first semiconductor devices are formed, wherein the plurality of first semiconductor devices are at least partially surrounded by a plurality of first dummy pads arranged in a ring configuration around the plurality of first semiconductor devices;

providing a second substrate on which a plurality of second semiconductor devices are formed, wherein the plurality of second semiconductor devices are at least partially surrounded by a plurality of second dummy pads arranged in a ring configuration around the plurality of second semiconductor devices;

roughening respective top surfaces of each of the plurality of first dummy pads;

roughening respective top surfaces of each of the plurality of second dummy pads;

providing a first bonding pad extending outwardly from the first substrate, the first bonding pad being at least partially surrounded by the plurality of first dummy pads;

providing a second bonding pad extending outwardly from the second substrate, the second bonding pad being at least partially surrounded by the plurality of second dummy pads, wherein the first and second bonding pads are located so as to be bonded with each other when the first and second substrates are coupled to one another;

coupling the first and second substrates by contacting respective top surface of the plurality of first and second dummy pads with each other so as to limit a lateral shift between the first and second substrates, wherein each of the top surfaces of the plurality of first and second dummy pads comprises plural peaks and valleys; and

providing a metal plate around an edge of a top surface of the second substrate so as to prevent lateral shifting between the first and second substrates after they are coupled to one another.

10. The method of claim 9, wherein before coupling the first and second substrates, the method further comprises:

flipping the second substrate and aligning the first semiconductor device with the second semiconductor device.

11. The method of claim 9, wherein the first semiconductor device comprises a micro-electro-mechanical system (MEMS) device.

12. The method of claim 9, wherein the second semiconductor device comprises a complementary metal-oxide-semiconductor (CMOS) circuit.

13. The method of claim 9, wherein the first dummy pads are disposed in a non-active region on the first substrate where the first semiconductor device is absent, and the second dummy pads are disposed in a non-active region on the second substrate where the second semiconductor device is absent.

14. The method of claim 9, wherein the coupling the first and second substrates further comprises:

bonding the first and second bonding pads to each other under an elevated temperature.

15. The method of claim 14, further comprising:

forming a eutectic layer on a top surface of the first bonding pad of the first substrate before the bonding process.

16. A method, comprising:

providing a first substrate on which a first semiconductor device is formed, wherein the first semiconductor device is at least partially surrounded by a plurality of first dummy pads;

providing a second substrate on which a second semiconductor device is formed, wherein the second semiconductor device is at least partially surrounded by a plurality of second dummy pads;

roughing respective top surfaces of the first dummy pads;

roughing respective top surfaces of the second dummy pads;

flipping the second substrate and aligning the first semiconductor device with the second semiconductor device;

providing a first bonding pad extending outwardly from the first substrate, the first bonding pad being at least partially surrounded by the plurality of first dummy pads;

providing a second bonding pad extending outwardly from the second substrate, the second bonding pad being at least partially surrounded by the plurality of second dummy pads, wherein the first and second bonding pads are located so as to be bonded with each other when the first and second substrates are coupled to one another;

coupling the first and second substrates by contacting the roughened top surfaces of respective first and second dummy pads with each other so as to limit a lateral shift between the first and second substrates; and

providing a metal plate around an edge of a top surface of the second substrate so as to prevent lateral shifting between the first and second substrates after they are coupled to one another.

17. The method of claim 16, wherein the first semiconductor device includes a micro-electro-mechanical system (MEMS) device.

18. The method of claim 16, wherein the second semiconductor device includes a complementary metal-oxide-semiconductor (CMOS) circuit.

19. The method of claim 16, wherein the coupling the first and second substrates further comprises:

bonding the first and second bonding pads to each other under an elevated temperature.

20. The method of claim 16, further comprising:

forming a eutectic layer on a top surface of the first bonding pad of the first substrate before the bonding process.