MEMS PACKAGE WITH ROUGHEND INTERFACE

• US 20180162720A1
• Filed: 12/06/2017
• Published: 06/14/2018
• Est. Priority Date: 12/13/2016
• Status: Active Grant

• Current Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Original Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Inventors: Cheng, Yu-Jui, Wang, I-Shi, Lee, Ren-Dou, Liu, Jen-Hao
• Granted Patent: US 10,710,872 B2
• Time in Patent Office: Days
• CPC Class Codes: B81B 7/007 Interconnections between the MEMS and external electrical signals
• CPC Class Codes: B81B 7/0077 Other packages not provided for in groups B81B7/0035 - B81B7/0074
• CPC Class Codes: B81B 7/02 containing distinct electrical or optical devices of particular relevance for their function, e.g. microelectro-mechanical systems [MEMS] B81B7/04 takes precedence
• CPC Class Codes: B81C 1/00238 Joining a substrate with an electronic processing unit and a substrate with a micromechanical structure
• CPC Class Codes: B81C 1/00269 Bonding of solid lids or wafers to the substrate
• CPC Class Codes: B81C 2203/019 characterised by the material or arrangement of seals between parts
• CPC Class Codes: B81C 2203/054 using structural alignment aids, e.g. spacers, interposers, male/female parts, rods or balls
• CPC Class Codes: B81C 2203/0735 Post-CMOS, i.e. forming the micromechanical structure after the CMOS circuit
• CPC Class Codes: B81C 2203/075 the electronic processing unit being integrated into an element of the micromechanical structure
• CPC Class Codes: B81C 3/005 Passive alignment, i.e. without a detection of the position of the elements or using only structural arrangements or thermodynamic forces
• CPC Class Codes: B81C 3/008 Aspects related to assembling from individually processed components, not covered by groups B81C3/001 - B81C3/002

Abstract

A method includes: providing a first substrate on which a plurality of first semiconductor devices is formed; providing a second substrate on which a plurality of second semiconductor devices is formed; and coupling the first and second substrates by contacting respective dummy pads of the first and second substrates, wherein at least one of the dummy pads of the first and second substrates comprises plural peaks and valleys.

Claims

1. A method, comprising:

providing a first substrate on which a plurality of first semiconductor devices is formed;

providing a second substrate on which a plurality of second semiconductor devices is formed; and

coupling the first and second substrates by contacting respective dummy pads of the first and second substrates,

wherein at least one of the dummy pads of the first and second substrates comprises plural peaks and valleys.

2. The method of claim 1, wherein the first semiconductor device comprises a micro-electro-mechanical system (MEMS) device.

3. The method of claim 1, wherein the second semiconductor device comprises a complementary metal-oxide-semiconductor (CMOS) circuit.

4. The method of claim 1, wherein before coupling the first and second substrates, the method further comprises:

forming a first plurality of peaks and valleys on a top surface of the dummy pads of the first substrate;

forming a second plurality of peaks and valleys on a top surface of the dummy pads of the second substrate; and

flipping the second substrate and aligning the first semiconductor device with the second semiconductor device.

5. The method of claim 1, wherein the dummy pad of the first substrate is disposed in a non-active region on the first substrate where the first semiconductor devices are absent.

6. The method of claim 1, wherein the dummy pad of the second substrate is disposed in a non-active region on the second substrate where the second semiconductor devices are absent.

7. The method of claim 1, wherein the dummy pad of the first substrate is formed as a ring-shape configuration that surrounds at least part of the first semiconductor devices.

8. The method of claim 1, wherein the dummy pad of the second substrate is formed as a ring-shape configuration that surrounds at least part of the second semiconductor devices.

9. The method of claim 1, wherein the coupling the first and second substrates further comprises:

bonding respective bonding pads of the first and second substrates under an elevated temperature.

10. The method of claim 9, further comprising:

forming a eutectic layer on a top surface of the bonding pad of the first substrate before the bonding process.

11. A method, comprising:

providing a first substrate on which a plurality of first semiconductor devices is formed, wherein the first semiconductor devices are at least partially surrounded by a plurality of first dummy pads;

providing a second substrate on which a plurality of second semiconductor devices is formed, wherein the second semiconductor devices are at least partially surrounded by a plurality of second dummy pads; and

coupling the first and second substrates by contacting the first and second dummy pads,

wherein at least one of the first and second dummy pads comprises plural peaks and valleys.

12. The method of claim 11, wherein before coupling the first and second substrates, the method further comprises:

forming a first plurality of peaks and valleys on a top surface of the first dummy pads;

forming a second plurality of peaks and valleys on a top surface of the second dummy pads; and

flipping the second substrate and aligning the first semiconductor device with the second semiconductor device.

13. The method of claim 11, wherein the first semiconductor device comprises a micro-electro-mechanical system (MEMS) device.

14. The method of claim 11, wherein the second semiconductor device comprises a complementary metal-oxide-semiconductor (CMOS) circuit.

15. The method of claim 11, wherein the first dummy pads are disposed in a non-active region on the first substrate where the first semiconductor device is absent, and the second dummy pads are disposed in a non-active region on the second substrate where the second semiconductor device is absent.

16. The method of claim 11, wherein the coupling the first and second substrates further comprises:

bonding respective bonding pads of the first and second substrates under an elevated temperature.

17. The method of claim 16, further comprising:

forming a eutectic layer on a top surface of the bonding pad of the first substrate before the bonding process.

18. A method, comprising:

providing a first substrate on which a first semiconductor device is formed, wherein the first semiconductor device is at least partially surrounded by a plurality of first dummy pads;

providing a second substrate on which a second semiconductor device is formed, wherein the second semiconductor device is at least partially surrounded by a plurality of second dummy pads;

roughing respective top surfaces of the first dummy pads;

roughing respective top surfaces of the second dummy pads;

flipping the second substrate and aligning the first semiconductor device with the second semiconductor device; and

coupling the first and second substrates by contacting the first and second dummy pads.

19. The method of claim 18, wherein the first semiconductor device includes a micro-electro-mechanical system (MEMS) device.

20. The method of claim 18, wherein the second semiconductor device includes a complementary metal-oxide-semiconductor (CMOS) circuit.