3D semiconductor device and structure

• US 10,840,239 B2
• Filed: 04/09/2017
• Issued: 11/17/2020
• Est. Priority Date: 08/26/2014
• Status: Active Grant

• Current Assignee: Monolithic 3D, Inc.
• Original Assignee: Monolithic 3D, Inc.
• Inventors: Or-Bach, Zvi, Cronquist, Brian
• Primary Examiner(s): Rahim, Nilufa
• Application Number:
  US15/482,787
• Publication Number:
  US 20170213821A1
• Time in Patent Office: 1,318 Days
• Field of Search: None
• CPC Class Codes: G11C 5/02 Disposition of storage elements, e.g. in the form of a matrix array
• CPC Class Codes: G11C 5/145 Applications of charge pumps; Boosted voltage circuits; Clamp circuits therefor G11C5/141 takes precedence
• CPC Class Codes: G11C 5/147 Voltage reference generators, voltage or current regulators; Internally lowered supply levels; Compensation for voltage drops G11C5/141 takes precedence
• CPC Class Codes: H01L 21/48 Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
• CPC Class Codes: H01L 21/6835 using temporarily an auxiliary support
• CPC Class Codes: H01L 21/76251 using bonding techniques
• CPC Class Codes: H01L 21/76254 with separation/delamination along an ion implanted layer, e.g. Smart-cut, Unibond
• CPC Class Codes: H01L 21/8221 Three dimensional integrated circuits stacked in different levels
• CPC Class Codes: H01L 21/823475 interconnection or wiring or contact manufacturing related aspects
• CPC Class Codes: H01L 21/823842 gate conductors with different gate conductor materials or different gate conductor implants, e.g. dual gate structures
• CPC Class Codes: H01L 21/823871 interconnection or wiring or contact manufacturing related aspects
• CPC Class Codes: H01L 2221/68345 used as a support during the manufacture of self supporting substrates
• CPC Class Codes: H01L 2221/68363 used in a transfer process involving transfer directly from an origin substrate to a target substrate without use of an intermediate handle substrate
• CPC Class Codes: H01L 2224/04042 Bonding areas specifically adapted for wire connectors, e.g. wirebond pads
• CPC Class Codes: H01L 2224/05599 Material
• CPC Class Codes: H01L 2224/45099 Material
• CPC Class Codes: H01L 2224/48091 Arched
• CPC Class Codes: H01L 23/367 Cooling facilitated by shape of device H01L23/38, H01L23/40, H01L23/42, H01L23/44, H01L23/46 take precedence
• CPC Class Codes: H01L 23/481 Internal lead connections, e.g. via connections, feedthrough structures
• CPC Class Codes: H01L 23/488 consisting of soldered or bonded constructions bump connectors H01L24/01
• CPC Class Codes: H01L 23/49827 : Via connections through the substrates, e.g. pins going through the substrate, coaxial cables H01L23/49822, H01L23/49833, H01L23/4985, H01L23/49861 take precedence
• CPC Class Codes: H01L 23/50 : for integrated circuit devices, e.g. power bus, number of leadsH01L23/482 - H01L23/498 take precedence
• CPC Class Codes: H01L 23/552 : Protection against radiation, e.g. light or electromagnetic waves
• CPC Class Codes: H01L 24/05 : of an individual bonding area
• CPC Class Codes: H01L 24/48 : of an individual wire connector
• CPC Class Codes: H01L 27/0222 : Charge pumping, substrate bias generation structures
• CPC Class Codes: H01L 27/0251 : for MOS devices
• CPC Class Codes: H01L 27/0688 : Integrated circuits having a three-dimensional layout
• CPC Class Codes: H01L 27/0694 : comprising components formed on opposite sides of a semiconductor substrate
• CPC Class Codes: H01L 27/088 : the components being field-effect transistors with insulated gate
• CPC Class Codes: H01L 27/092 : complementary MIS field-effect transistors
• CPC Class Codes: H01L 27/0922 : Combination of complementary transistors having a different structure, e.g. stacked CMOS, high-voltage and low-voltage CMOS
• CPC Class Codes: H01L 27/0924 : including transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 29/66545 : using a dummy, i.e. replacement gate in a process wherein at least a part of the final gate is self aligned to the dummy gate
• CPC Class Codes: H01L 29/66628 : recessing the gate by forming single crystalline semiconductor material at the source or drain location
• CPC Class Codes: H01L 2924/00 : Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/00014 : the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/13091 : Metal-Oxide-Semiconductor Field-Effect Transistor [MOSFET]
• CPC Class Codes: H01L 2924/14 : Integrated circuits
• CPC Class Codes: H01L 2924/3025 : Electromagnetic shielding
• CPC Class Codes: H10B 12/34 : the transistor being at least partially in a trench in the substrate

Abstract

A 3D integrated circuit device, including: a first layer including first transistors, overlaid by a second layer including second transistors, overlaid by a third layer including third transistors, where the first layer, the second layer and the third layer are each thinner than 2 microns, where the first layer includes first circuits including at least one of the first transistors, where the second layer includes second circuits including at least one of the second transistors, and where the third layer includes a charge pump circuit and control circuits to control the first circuits and the second circuits.

Claims

1. A 3D integrated circuit device, the device comprising:

a first level comprising first transistors, overlaid by a second level comprising second transistors, overlaid by a third level comprising third transistors, said third transistors each comprise a single crystal channel,

wherein said second level is thinner than 0.4 microns,

wherein said first level comprises a first array of first memory cells, each of said first memory cells comprising at least one of said first transistors,

wherein said second level comprises a second array of second memory cells, each of said second memory cells comprising at least one of said second transistors, and

wherein said third level comprises a charge pump circuit and control circuits to control said charge pump circuit; and

a plurality of connections connecting from said third transistors to said second transistors forming a multiplicity of connection paths,

wherein said multiplicity of connection paths comprise copper to copper bonded links.

2. The device according to claim 1,

wherein said second transistors are self-aligned to said first transistors, being processed following the same lithography step.

3. The device according to claim 1, further comprising:

memory control circuits,

wherein said memory control circuits comprise a plurality of said third transistors.

4. The device according to claim 1,

wherein at least one of said second transistors comprises SiGe.

5. The device according to claim 1,

wherein said third level comprises an Electro Static Discharge (“

ESD”

) circuit.

6. The device according to claim 1,

wherein an area I/O circuit comprises at least one of said third transistors.

7. The device according to claim 1,

wherein at least one of said second transistors is a vertical transistor.

8. A 3D integrated circuit device, the device comprising:

a first level comprising first transistors, overlaid by a second level comprising second transistors, overlaid by a third level comprising third transistors,

wherein said second level is thinner than 0.4 microns,

wherein said second level comprises a second array of second memory cells, each of said second memory cells comprising at least one of said second transistors, and

wherein said third level comprises a charge pump circuit and control circuits to control said charge pump circuit, and an electrostatic discharge (“

ESD”

) structure, and

a plurality of connections connecting from said third transistors to said second transistors forming a multiplicity of connection paths,

wherein said multiplicity of connection paths comprise copper to copper bonded links.

9. The device according to claim 8,

wherein said second transistors are self-aligned to said first transistors, being processed following the same lithography step.

10. The device according to claim 8, further comprising:

memory control circuits,

wherein said memory control circuits comprise a plurality of said third transistors.

11. The device according to claim 8,

wherein at least one of said second transistors comprises SiGe.

12. The device according to claim 8,

wherein at least one of said second transistors is a vertical transistor.

13. The device according to claim 8,

wherein an area I/O circuit comprises at least one of said third transistors.

14. A 3D integrated circuit device, the device comprising:

a first level comprising first transistors, overlaid by a second level comprising second transistors, overlaid by a third level comprising third transistors,

wherein said second level is thinner than 0.4 microns,

wherein said first level comprises a first array of first memory cells, each of said first memory cells comprising at least one of said first transistors,

wherein said second level comprises a second array of second memory cells, each of said second memory cells comprising at least one of said second transistors, and

wherein said third level comprises a charge pump circuit and control circuits to control said charge pump circuit; and

a plurality of connections connecting from said third transistors to said second transistors forming a multiplicity of connection paths,

wherein said multiplicity of connection paths comprise copper to copper bonded links.

15. The device according to claim 14,

wherein said second transistors are self-aligned to said first transistors.

16. The device according to claim 14, further comprising:

a memory periphery circuit comprising at least one of said third transistors,

wherein said memory periphery circuit is controlling at least one of said first memory cells and at least one of said second memory cells.

17. The device according to claim 14,

wherein at least one of said second transistors comprises SiGe.

18. The device according to claim 14,

wherein said third level comprises an Electro Static Discharge (“

ESD”

) circuit.

19. The device according to claim 14,

wherein an area I/O circuit comprises at least one of said third transistors.

20. The device according to claim 14,

wherein at least one of said second transistors is a vertical transistor.