Dual-gate thin film transistor, manufacturing method thereof, array substrate and display device

  • US 11,049,975 B2
  • Filed: 08/21/2017
  • Issued: 06/29/2021
  • Est. Priority Date: 01/05/2017
  • Status: Active Grant
First Claim
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1. A dual-gate thin film transistor, comprising:

  • a base substrate;

    a first gate disposed on the base substrate;

    a first gate insulating layer disposed on the first gate, the first gate insulating layer comprising a first via hole exposing a portion of the first gate;

    an active layer disposed on the first gate insulating layer, the active layer and the first gate at least partially overlapping with each other in a direction perpendicular to the base substrate;

    a second gate insulating layer disposed on the active layer;

    a first electrode and a second electrode, which are disposed in contact with the active layer;

    a second gate disposed on the second gate insulating layer, the second gate and the active layer at least partially overlapping with each other in a direction perpendicular to the base substrate, and the second gate, the first electrode and the second electrode formed in a same level;

    a connection electrode electrically connected with the second gate and electrically connected with the first gate through the first via hole; and

    a first passivation layer, wherein the first passivation layer is disposed on the second gate, the first passivation layer comprises a third via hole exposing the first via hole, and an area of an orthographic projection of the first via hole on the base substrate is larger than an area of an orthographic projection of the third via hole on the base substrate, and the orthographic projection of the third via hole on the base substrate is within the orthographic projection of the first via hole on the base substrate.

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