Dual-gate thin film transistor, manufacturing method thereof, array substrate and display device

• US 11,049,975 B2
• Filed: 08/21/2017
• Issued: 06/29/2021
• Est. Priority Date: 01/05/2017
• Status: Active Grant

• Current Assignee: Beijing BOE Display Technology Co Ltd (BOE Technology Group Co., Ltd.), BOE Technology Group Co., Ltd.
• Original Assignee: BOE Technology Group Co., Ltd.
• Inventors: Qu, Lianjie, Bai, Jinchao
• Primary Examiner(s): Choi, Calvin Y
• Application Number:
  US15/780,926
• Publication Number:
  US 20200287052A1
• Time in Patent Office: 1,408 Days
• CPC Class Codes: H01L 29/6675 Amorphous silicon or polysilicon transistors
• CPC Class Codes: H01L 29/66969 of devices having semiconductor bodies not comprising group 14 or group 13/15 materials comprising selenium or tellurium in uncombined form other than as impurities in semiconductor bodies of other materials, comprising cuprous oxide or cuprous iodide H01L21/02365
• CPC Class Codes: H01L 29/78645 with multiple gate
• CPC Class Codes: H01L 29/78648 arranged on opposing sides of the channel
• CPC Class Codes: H01L 29/78663 Amorphous silicon transistors
• CPC Class Codes: H01L 33/42 Transparent materials
• CPC Class Codes: H10K 2102/101 comprising transparent conductive oxides [TCO]
• CPC Class Codes: H10K 50/84 Passivation; Containers; Encapsulations
• CPC Class Codes: H10K 59/1213 the pixel elements being TFTs
• CPC Class Codes: H10K 59/131 Interconnections, e.g. wiring lines or terminals
• CPC Class Codes: H10K 71/00 Manufacture or treatment specially adapted for the organic devices covered by this subclass

Abstract

A dual-gate thin film transistor, a manufacturing method thereof, an array substrate and a display device are provided. The dual-gate thin film transistor includes: a base substrate and a first gate, a first gate insulating layer, an active layer, a second gate insulating layer, a first electrode, a second electrode, a second gate and a connection electrode, formed on the base substrate. The second gate, the first electrode and the second electrode are formed on the same level. The first gate insulating layer includes a first via hole exposing a portion of the first gate, and the connection electrode is electrically connected with the second gate and is electrically connected with the first gate through the first via hole.

Claims

1. A dual-gate thin film transistor, comprising:

a base substrate;

a first gate disposed on the base substrate;

a first gate insulating layer disposed on the first gate, the first gate insulating layer comprising a first via hole exposing a portion of the first gate;

an active layer disposed on the first gate insulating layer, the active layer and the first gate at least partially overlapping with each other in a direction perpendicular to the base substrate;

a second gate insulating layer disposed on the active layer;

a first electrode and a second electrode, which are disposed in contact with the active layer;

a second gate disposed on the second gate insulating layer, the second gate and the active layer at least partially overlapping with each other in a direction perpendicular to the base substrate, and the second gate, the first electrode and the second electrode formed in a same level;

a connection electrode electrically connected with the second gate and electrically connected with the first gate through the first via hole; and

a first passivation layer, wherein the first passivation layer is disposed on the second gate, the first passivation layer comprises a third via hole exposing the first via hole, and an area of an orthographic projection of the first via hole on the base substrate is larger than an area of an orthographic projection of the third via hole on the base substrate, and the orthographic projection of the third via hole on the base substrate is within the orthographic projection of the first via hole on the base substrate.

2. The dual-gate thin film transistor according to claim 1, wherein the first passivation layer comprises a second via hole exposing a portion of the second gate, the connection electrode is disposed on the first passivation layer, is electrically connected with the second gate through the second via hole and electrically connected with the first gate through the third via hole and the first via hole.

3. The dual-gate thin film transistor according to claim 1, wherein the first electrode and the second electrode are disposed on the second gate insulating layer, the second gate insulating layer comprises a fourth via hole and a fifth via hole which expose at least a portion of the active layer and are located on respective sides of the second gate, the first electrode is electrically connected with the active layer through the fourth via hole, and the second electrode is electrically connected with the active layer through the fifth via hole.

4. The dual-gate thin film transistor according to claim 1, wherein the second gate insulating layer partially covers the active layer, in a direction parallel to the base substrate, on both sides of the second gate, the active layer has a first end and a second end which are at least partially uncovered by the second gate insulating layer, the first electrode overlaps with the active layer through the first end, and the second electrode overlaps with the active layer through the second end.

5. The dual-gate thin film transistor according to claim 1, wherein the connection electrode is made of a transparent conductive material.

6. The dual-gate thin film transistor according to claim 1, wherein the second gate, the first electrode and the second electrode can be made of one or more selected from a group consisting of molybdenum, molybdenum alloy, copper, copper alloy, aluminum, aluminum alloy, titanium and titanium alloy.

7. The dual-gate thin film transistor according to claim 1, wherein the active layer is an amorphous silicon layer, a polysilicon layer, or a metal oxide semiconductor layer.

8. An array substrate, comprising the dual-gate thin film transistor according to claim 1.

9. The array substrate according to claim 8, further comprising a gate line disposed on the base substrate, wherein

the gate line is electrically connected with the first gate, and the connection electrode is electrically connected with the second gate and is electrically connected with the gate line through the first via hole.

10. The array substrate according to claim 8, further comprising at least one of a pixel electrode and a common electrode, wherein

at least one of the pixel electrode and the common electrode is formed on a same level as the connection electrode.

11. The array substrate according to claim 10, wherein the common electrode and the pixel electrode are formed on a same level or on different levels.

15. A display device, comprising the array substrate according to claim 8.

20. The dual-gate thin film transistor according to claim 2, wherein the first electrode and the second electrode are disposed on the second gate insulating layer, the second gate insulating layer comprises a fourth via hole and a fifth via hole which expose at least a portion of the active layer and are located on respective sides of the second gate, the first electrode is electrically connected with the active layer through the fourth via hole, and the second electrode is electrically connected with the active layer through the fifth via hole.

12. A method for manufacturing a dual-gate thin film transistor, comprising:

providing a base substrate;

forming a first gate on the base substrate;

forming a first gate insulating layer on the first gate;

forming an active layer on the first gate insulating layer, the active layer partially overlapping the first gate in a direction perpendicular to the base substrate;

forming a second gate insulating layer on the active layer;

forming a second gate, a first electrode and a second electrode through one conductive layer, wherein the second gate is disposed on the second gate insulating layer and partially overlaps the active layer in a direction perpendicular to the base substrate, and both the first electrode and the second electrode are in contact with the active layer; and

forming a connection electrode, which is electrically connected with the second gate and is electrically connected with the first gate;

forming a first passivation layer;

forming a first via hole exposing a portion of the first gate in the first gate insulating layer; and

forming a third via hole exposing a portion of the first via hole in the first passivation layer, wherein an area of an orthographic projection of the first via hole on the base substrate is larger than an area of an orthographic projection of the third via hole on the base substrate, and the orthographic projection of the third via hole on the base substrate is within the orthographic projection of the first via hole on the base substrate.

13. The method according to claim 12, further comprising:

forming a second via hole in the first passivation layer wherein the second via hole at least partially exposes the second gate, and the connection electrode is electrically connected with the second gate through the second via hole and is electrically connected with the first gate through the third via hole and the first via hole.

14. The method according to claim 12, wherein the connection electrode is made of a transparent conductive film.

16. The method according to claim 13, wherein the first via and the third via are formed through one etching process, or the first via and the third via are formed through different etching processes.

17. The method according to claim 12, wherein the second gate insulating layer covers a portion of the active layer, two opposite ends of the active layer are exposed, and the first electrode and the second electrode are in direct contact with the exposed ends of the active layer respectively.

18. The method according to claim 12, wherein the second gate insulating layer covers entirety of the active layer, the method further comprising forming a fourth via and a fifth via in the second gate insulating layer, the first electrode electrically connected to the active layer through the fourth via and the second electrode electrically connected to the active layer through the fifth via.

19. The method according to claim 12, wherein the second gate insulating layer covers a portion of the active layer and one end of the active layer is exposed, the connection electrode is in direct contact with the second gate and is extended on the second gate insulating layer and the first gate insulating layer, and is electrically connected to the first gate through the first via hole in first gate insulating layer.