Circuit for CMOS based resistive processing unit

• US 11,055,611 B2
• Filed: 11/21/2017
• Issued: 07/06/2021
• Est. Priority Date: 06/30/2017
• Status: Active Grant

• Current Assignee: International Business Machines Corporation
• Original Assignee: International Business Machines Corporation
• Inventors: Li, Yulong, Solomon, Paul, Leobandung, Effendi, Yeh, Chun-Chen, Kim, Seyoung
• Primary Examiner(s): Lamardo, Viker A
• Application Number:
  US15/820,114
• Publication Number:
  US 20190005382A1
• Time in Patent Office: 1,323 Days
• Field of Search: 706 23
• CPC Class Codes: G06F 17/16 Matrix or vector computation , e.g. matrix-matrix or matrix-vector multiplication, matrix factorization matrix transposition G06F7/78
• CPC Class Codes: G06N 3/065 Analogue means
• CPC Class Codes: G06N 3/08 Learning methods
• CPC Class Codes: G06N 3/084 Backpropagation, e.g. using gradient descent

Abstract

A CMOS-based resistive processing unit (RPU) and method for a neural network. The RPU includes a capacitor device configured to store a charge representing a weight value associated with a neural network circuit operation. A current source Field Effect Transistor (FET) device is operatively connected to the capacitor device for increasing a charge on the capacitor. A current sink FET device operatively connected to the capacitor device is configured for decreasing the stored capacitor charge. An analog weight update circuit receives one or more update signals generated in conjunction with the neural network circuit operation, the analog weight update circuit controlling the current source FET device and the current sink FET device to provide either a determined amount of current to increase the stored charge on the capacitor device, or sink a determined amount of current to decrease the stored charge on the capacitor device.

Claims

1. A method of operating a resistive processing unit of a neural network, said method comprising:

storing a charge on a complementary-metal-oxide semiconductor (CMOS) capacitor device, said charge representing a weight value associated with a neural network circuit;

receiving at a first inverter circuit a first analog voltage signal;

receiving at a second inverter circuit a second analog voltage signal;

inputting at said first inverter circuit a pulse signal of pre-determined pulse width;

generating, from said input pulse signal, a further pulsed signal for input to said second inverter circuit;

generating, in response to said received first analog voltage signal and said pulse signal, a first analog output signal at said first inverter circuit, said first analog output signal controlling a current source Field Effect Transistor (FET) operatively connected to said CMOS capacitor device to provide a charging current to increase a charge stored at the CMOS capacitor device; and

generating, in response to said received second analog voltage signal and said further pulsed signal, a second analog output signal at said second inverter circuit, said second analog output signal controlling a current sink FET operatively connected to said CMOS capacitor device to receive a current discharging from the CMOS capacitor device to decrease a charge stored at the CMOS capacitor device.

2. The method as claimed in Claim 1, wherein said neural network circuit performs a vector-vector outer product operation, said first analog voltage signal representing a portion of first vector involved in said neural network vector-vector outer product operation, and said second analog voltage signal representing a portion of a second vector involved in said neural network vector-vector outer product operation.

3. The method as claimed in Claim 2, wherein said neural network circuit further updates a capacitor weight associated with said neural network vector-vector outer product operation.

4. The method as claimed in Claim 2, said method further comprising:

biasing said first inverter circuit to operate at voltage levels between a value of said received first analog voltage signal and a voltage supply value of equal or greater value; and

biasing said second inverter circuit to operate at voltage levels between a value of said received second analog voltage signal and a ground potential at a same or lesser value than said second analog voltage signal value.

5. The method as claimed in Claim 4, wherein said ground potential of lesser value is a zero or negative ground potential.

6. The method as claimed in claim 4, wherein both said first timing pulse and second timing pulse are a respective first pulse train and a second pulse train, said method further comprising:

generating both said first pulse train and said second pulse train and a combination of respective first vector voltage and second vector voltage values for providing a CMOS capacitor device charge increase operation and CMOS capacitor device charge decrease operation in symmetrical fashion over a period of time.

7. The method as claimed in Claim 4, further comprising:

receiving, at an input to a third inverter circuit said first timing pulse, and generating as an output said further pulsed signal for input to said second inverter circuit.

8. The method as claimed in Claim 7, where said first inverter circuit comprises

a P-channel MOS FET device (PMOS device) having a gate, drain and source terminals;

and

a N-channel MOS FET device (NMOS device) having a gate, drain and source terminals, wherein said gate terminal of said PMOS device is connected to said gate terminal of said NMOS device, said connected gate terminals configured to receive said first timing pulse, and

wherein a drain terminal of said PMOS FET is connected to said drain terminal of said NMOS FET, said connected PMOS FET drain and NMOS FET drain terminals being electrically connected to a gate terminal of said current source FET.

9. The method as claimed in Claim 8, where said second inverter circuit comprises:

a P-channel MOS FET device (PMOS device) having a gate, drain and source terminals;

a N-channel MOS FET device (NMOS device) having a gate, drain and source terminals, wherein said gate terminal of said PMOS device being electrically connected to said gate terminal of said NMOS device, and

wherein a drain terminal of said PMOS device is connected to said drain terminal of said NMOS device, said connected PMOS device drain terminal and NMOS device drain terminal being electrically connected to a gate terminal of said current sink FET.

10. The method as claimed in Claim 9, where said third inverter circuit comprises:

a P-channel MOS FET device (PMOS device) having a gate, drain and source terminals;

a N-channel MOS FET device (NMOS device) having a gate, drain and source terminals, wherein said gate terminal of said PMOS device is connected to said gate terminal of said NMOS device, said connected gate terminals configured to receive said first timing pulse; and

wherein a drain terminal of said PMOS device is connected to said drain terminal of said NMOS device, said connected PMOS device drain terminal and NMOS device drain terminal being electrically connected to said electrically connected gate terminals of said second inverter circuit.

11. The method as claimed in claim 1, wherein said first analog control signal and said pulse signal controls an amount of current flow through said current source FET;

and said second analog control signal and further pulsed signal controls an amount of current flow through said current sink FET.

12. The method as claimed in claim 2, wherein said neural network circuit comprises a crossbar matrix array circuit, said neural network vector-vector outer product operation comprising:

performing a multiplication operation and an incremental weight update operation locally at a cross-point of said crossbar matrix array circuit.

13. The method as claimed in claim 12, wherein for said neural network vector-vector outer product operation, said method comprises:

applying a voltage on each column (or row) and collecting a current on each row (or column) at said cross-point.