CIRCUIT FOR CMOS BASED RESISTIVE PROCESSING UNIT
First Claim
1. A method of operating a resistive processing unit of a neural network, said method comprising:
- storing a charge on a complementary-metal-oxide semiconductor (CMOS) capacitor device, said charge representing a weight value associated with a neural network circuit operation;
receiving at a first analog processing circuit a first analog voltage signal;
receiving at a second analog processing circuit a second analog voltage signal;
inputting at said first analog processing circuit a pulse signal of pre-determined pulse width during said neural network circuit operation,generating, from said input pulse signal, a further pulsed signal for input to said second analog processing circuit;
generating a first analog output signal at said first analog processing circuit, andgenerating a second analog output signal at said second analog processing circuit, said first analog and second analog output signals of values for controlling a charging circuit operatively connected to said capacitor device and a discharging circuit operatively connected to said capacitor device to respectively increase a charge stored on said capacitor device, or decrease a charge stored on said capacitor device.
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Accused Products
Abstract
A CMOS-based resistive processing unit (RPU) and method for a neural network. The RPU includes a capacitor device configured to store a charge representing a weight value associated with a neural network circuit operation. A current source Field Effect Transistor (FET) device is operatively connected to the capacitor device for increasing a charge on the capacitor. A current sink FET device operatively connected to the capacitor device is configured for decreasing the stored capacitor charge. An analog weight update circuit receives one or more update signals generated in conjunction with the neural network circuit operation, the analog weight update circuit controlling the current source FET device and the current sink FET device to provide either a determined amount of current to increase the stored charge on the capacitor device, or sink a determined amount of current to decrease the stored charge on the capacitor device.
3 Citations
10 Claims
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1. A method of operating a resistive processing unit of a neural network, said method comprising:
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storing a charge on a complementary-metal-oxide semiconductor (CMOS) capacitor device, said charge representing a weight value associated with a neural network circuit operation; receiving at a first analog processing circuit a first analog voltage signal; receiving at a second analog processing circuit a second analog voltage signal; inputting at said first analog processing circuit a pulse signal of pre-determined pulse width during said neural network circuit operation, generating, from said input pulse signal, a further pulsed signal for input to said second analog processing circuit; generating a first analog output signal at said first analog processing circuit, and generating a second analog output signal at said second analog processing circuit, said first analog and second analog output signals of values for controlling a charging circuit operatively connected to said capacitor device and a discharging circuit operatively connected to said capacitor device to respectively increase a charge stored on said capacitor device, or decrease a charge stored on said capacitor device. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10)
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Specification