Method for fabricating a semiconductor device comprising an oxide semiconductor

• US 11,107,840 B2
• Filed: 02/03/2020
• Issued: 08/31/2021
• Est. Priority Date: 11/06/2009
• Status: Active Grant

• Current Assignee: Semiconductor Energy Laboratory Co., Ltd.
• Original Assignee: Semiconductor Energy Laboratory Co., Ltd.
• Inventors: Yamazaki, Shunpei, Koyama, Jun, Miyake, Hiroyuki
• Primary Examiner(s): Bradley, Stephen M
• Application Number:
  US16/780,034
• Publication Number:
  US 20200176486A1
• Time in Patent Office: 575 Days
• CPC Class Codes: G09G 2310/0267 Details of drivers for scan electrodes, other than drivers for liquid crystal, plasma or OLED displays
• CPC Class Codes: G09G 2310/0275 Details of drivers for data electrodes, other than drivers for liquid crystal, plasma or OLED displays, not related to handling digital grey scale data or to communication of data to the pixels by means of a current
• CPC Class Codes: G09G 2310/0286 Details of a shift registers arranged for use in a driving circuit
• CPC Class Codes: G09G 3/20 for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
• CPC Class Codes: G11C 19/28 using semiconductor elements G11C19/14, G11C19/36 take precedence
• CPC Class Codes: H01L 27/1225 with semiconductor materials not belonging to the group IV of the periodic table, e.g. InGaZnO
• CPC Class Codes: H01L 27/1229 with different crystal properties within a device or between different devices
• CPC Class Codes: H01L 27/1251 comprising TFTs having a different architecture, e.g. top- and bottom gate TFTs
• CPC Class Codes: H01L 29/045 by their particular orientation of crystalline planes
• CPC Class Codes: H01L 29/1033 with insulated gate, e.g. characterised by the length, the width, the geometric contour or the doping structure with channel and gate aligned in the lengthwise direction H01L29/42376; with buried channel H01L29/7838
• CPC Class Codes: H01L 29/24 including, apart from doping materials or other impurities, only semiconductor materials not provided for in groups H01L29/16, H01L29/18, H01L29/20, H01L29/22 including organic materials H10K99/00
• CPC Class Codes: H01L 29/247 Amorphous materials
• CPC Class Codes: H01L 29/41733 for thin film transistors with insulated gate
• CPC Class Codes: H01L 29/42372 characterised by the conducting layer, e.g. the length, the sectional shape or the lay-out H01L29/42324 takes precedence
• CPC Class Codes: H01L 29/45 Ohmic electrodes
• CPC Class Codes: H01L 29/4908 for thin film semiconductor, e.g. gate of TFT
• CPC Class Codes: H01L 29/78609 for preventing leakage current H01L29/78618 takes precedence
• CPC Class Codes: H01L 29/78648 arranged on opposing sides of the channel
• CPC Class Codes: H01L 29/7869 having a semiconductor body comprising an oxide semiconductor material, e.g. zinc oxide, copper aluminium oxide, cadmium stannate
• CPC Class Codes: H01L 29/78693 the semiconducting oxide being amorphous
• CPC Class Codes: H10K 59/1213 : the pixel elements being TFTs

Abstract

An object of an embodiment of the present invention is to manufacture a semiconductor device with high display quality and high reliability, which includes a pixel portion and a driver circuit portion capable of high-speed operation over one substrate, using transistors having favorable electric characteristics and high reliability as switching elements. Two kinds of transistors, in each of which an oxide semiconductor layer including a crystalline region on one surface side is used as an active layer, are formed in a driver circuit portion and a pixel portion. Electric characteristics of the transistors can be selected by choosing the position of the gate electrode layer which determines the position of the channel. Thus, a semiconductor device including a driver circuit portion capable of high-speed operation and a pixel portion over one substrate can be manufactured.

Claims

1. A method for fabricating a semiconductor device comprising the steps of:

forming a gate electrode layer;

forming a gate insulating layer;

forming an oxide semiconductor layer, in which a channel is formed, overlapping with the gate electrode layer with the gate insulating layer provided therebetween;

forming a first insulating layer over the oxide semiconductor layer;

forming a second insulating layer over the first insulating layer;

forming a third insulating layer over the second insulating layer; and

forming a source electrode layer and a drain electrode layer electrically connected to the oxide semiconductor layer,

wherein the oxide semiconductor layer comprises indium, gallium, and zinc,

wherein the oxide semiconductor layer is formed by a sputtering method,

wherein the oxide semiconductor layer comprises a crystal region including a crystal with a particle size greater than or equal to 1 nm and less than or equal to 20 nm in a surface portion,

wherein the source electrode layer or the drain electrode layer is in contact with a side surface of the oxide semiconductor layer,

wherein the source electrode layer and the drain electrode layer overlap with the gate electrode layer, and

wherein the crystal region has c-axis alignment.

2. The method for fabricating a semiconductor device according to claim 1, wherein the crystal is a nanocrystal.

3. The method for fabricating a semiconductor device according to claim 1, wherein an end portion of the oxide semiconductor layer has a tapered shape.

4. The method for fabricating a semiconductor device according to claim 1, wherein the gate electrode layer contains a metal material selected from Al, Cr, Ta, Ti, Mo, and W.

5. The method for fabricating a semiconductor device according to claim 1, wherein the source electrode layer and the drain electrode layer contain a metal material selected from Al, Cu, Cr, Ta, Ti, Mo, and W.

6. The method for fabricating a semiconductor device according to claim 1, wherein the oxide semiconductor layer has a thickness of greater than or equal to 5 nm and less than or equal to 200 nm.

7. The method for fabricating a semiconductor device according to claim 1,

wherein the gate electrode layer is provided under the oxide semiconductor layer, and

wherein the gate insulating layer contains silicon oxide.

8. The method for fabricating a semiconductor device according to claim 1, further comprising the steps of:

forming an opening in the first insulating layer; and

forming an electrode of a display element over the third insulating layer,

wherein the electrode of the display element is electrically connected to the source electrode layer or the drain electrode layer through the opening.

9. A method for fabricating a semiconductor device comprising the steps of:

forming a substrate;

forming a gate electrode layer;

forming a gate insulating layer over the gate electrode layer;

forming an oxide semiconductor layer, in which a channel is formed, overlapping with the gate electrode layer with the gate insulating layer provided therebetween;

forming a first insulating layer over the oxide semiconductor layer;

forming a second insulating layer over the first insulating layer;

forming a third insulating layer over the second insulating layer; and

forming a source electrode layer and a drain electrode layer electrically connected to the oxide semiconductor layer,

wherein the oxide semiconductor layer comprises indium, gallium, and zinc,

wherein the oxide semiconductor layer is formed by a sputtering method,

wherein the oxide semiconductor layer comprises a crystal region including a crystal with a particle size greater than or equal to 1 nm and less than or equal to 20 nm in a surface portion,

wherein the source electrode layer or the drain electrode layer is in contact with a side surface of the oxide semiconductor layer,

wherein the source electrode layer and the drain electrode layer overlap with the gate electrode layer, and

wherein the crystal region has c-axis alignment.

10. The method for fabricating a semiconductor device according to claim 9, wherein the crystal is a nanocrystal.

11. The method for fabricating a semiconductor device according to claim 9, wherein an end portion of the oxide semiconductor layer has a tapered shape.

12. The method for fabricating a semiconductor device according to claim 9, wherein the gate electrode layer contains a metal material selected from Al, Cr, Ta, Ti, Mo, and W.

13. The method for fabricating a semiconductor device according to claim 9, wherein the source electrode layer and the drain electrode layer contain a metal material selected from Al, Cu, Cr, Ta, Ti, Mo, and W.

14. The method for fabricating a semiconductor device according to claim 9, wherein the oxide semiconductor layer has a thickness of greater than or equal to 5 nm and less than or equal to 200 nm.

15. The method for fabricating a semiconductor device according to claim 9,

wherein the gate electrode layer is provided under the oxide semiconductor layer, and

wherein the gate insulating layer contains silicon oxide.

16. The method for fabricating a semiconductor device according to claim 9, further comprising the steps of:

forming an opening in the first insulating layer; and

forming an electrode of a display element over the third insulating layer,

wherein the electrode of the display element is electrically connected to the source electrode layer or the drain electrode layer through the opening.