Ephemeral storage elements, circuits, and systems

• US 11,783,898 B2
• Filed: 09/17/2015
• Issued: 10/10/2023
• Est. Priority Date: 09/18/2014
• Status: Active Grant

• Current Assignee: Jonker LLC
• Original Assignee: Jonker LLC
• Inventors: Gross, John Nicholas, Liu, David K. Y.
• Primary Examiner(s): King, Douglas
• Application Number:
  US14/857,275
• Publication Number:
  US 20160086670A1
• Time in Patent Office: 2,945 Days
• CPC Class Codes: G11C 16/0483 comprising cells having several storage transistors connected in series
• CPC Class Codes: G11C 16/14 Circuits for erasing electrically, e.g. erase voltage switching circuits
• CPC Class Codes: G11C 16/26 Sensing or reading circuits; Data output circuits
• CPC Class Codes: G11C 16/32 Timing circuits
• CPC Class Codes: G11C 16/3431 Circuits or methods to detect disturbed nonvolatile memory cells, e.g. which still read as programmed but with threshold less than the program verify threshold or read as erased but with threshold greater than the erase verify threshold, and to reverse the disturbance via a refreshing programming or erasing step
• CPC Class Codes: H10B 51/30 characterised by the memory core region

Abstract

An array of programmable non-volatile devices are is adapted such that their logic state is controllably altered over time by quiescent changes, slow controlled changes, scheduled changes, or some combination thereof imposed at a physical level. This allows for improved security and privacy for data to be permanently deleted. In some applications a data refresh and/or automatic backup can be implemented as well.

Claims

1. A memory device on an integrated circuit adapted with ephemeral data retention capability comprising:

an array of charge storage elements;

wherein said charge storage element is characterized by an inherent leakage current and is configurable;

to store a first amount of charge corresponding to a first unprogrammed state representing a first data value; and

to store a second amount of charge corresponding to a second programmed state representing a second data value;

a programming control circuit configured;

to set said array of charge elements to said second programmed state representing said second data value based on a first write operation;

to initiate and control a first scheduled erase operation in which all charge is removed from a selected charge storage element over a first predetermined erase period;

to initiate and control a second separate slower erase operation on said array, during which a controlled erase charge is actively removed from selected charge storage elements over second predetermined erase periods that are longer than said first determined period and in the absence of a new second write operation for such array;

wherein said programming control circuit is adapted to actively impose erase bias voltages to said array of charge storage elements during said controlled predetermined period so that said controlled erase charge is removed from such elements in addition to charge lost to leakage current by such elements.

2. The device of claim 1 wherein said programming control circuit is configured so that said erase operation can erase said charge storage elements and set a new unprogrammed state by setting respective threshold voltages of said charge storage elements to a first threshold voltage.

3. The device of claim 2 wherein a new second write operation can set a new programmed state by setting the respective threshold voltages to a second threshold voltage higher than said first threshold voltage.

4. The device of claim 1 wherein said predetermined erase periods can be controlled by a software application.

5. The device of claim 1 wherein said predetermined erase periods are fixed in physical form on the integrated circuit.

6. The device of claim 1 wherein said erase operation cannot be disabled by any control signal provided to the integrated circuit and occurs automatically to implement a forced erase of any array data.

7. The device of claim 1 further including an alert circuit for generating an alert at a target time indicating an impending erase.

8. The device of claim 1 wherein the programming control circuit is configured to cause holes to be injected into a floating gate of the selected charge storage elements.

9. The device of claim 1 wherein the programming control circuit is configured to cause apply the smallest possible bias required to remove charge from the selected charge storage elements during said controlled predetermined period to achieve a target data retention time.

10. The device of claim 1 wherein the selected charge storage elements are part of a secure storage area on the integrated circuit.

11. The device of claim 1 wherein the programming control circuit is configured to cause Fowler-Nordheim tunneling to remove said charge during said controlled predetermined period.

12. The device of claim 1 wherein the programming control circuit is configured to cause a negative erase voltage to be applied to a control gate of the selected charge storage elements and a positive voltage to a drain of said selected charge storage elements to remove said charge during said controlled predetermined period.

13. The device of claim 1 wherein a refresh operation is implemented by the programming control circuit with timing based on a target data retention characteristic of said charge storage element.

14. A memory device on an integrated circuit adapted with ephemeral data retention capability comprising:

an array of charge storage elements;

wherein each charge storage element in said array is characterized by an inherent leakage current and is configurable;

to store a first amount of charge corresponding to a first state corresponding to a first state representing a first data value; and

to store a second amount of charge corresponding to a second state representing a second data value;

a programming control circuit configured;

to program said array of charge storage elements to said second data value based on a first write operation;

to initiate and control a slow erase operation on said array, including at least a first mode in which a controlled erase charge is actively removed from a selected charge storage element over a controlled predetermined period and in the absence of a new second write operation for such selected charge storage element;

to actively impose erase bias voltages to said array of charge storage elements during said controlled predetermined period so that said controlled erase charge is removed from such elements in addition to charge lost to leakage current by such elements; and

to apply the smallest possible bias required to remove charge from the selected charge storage elements during said controlled predetermined period to achieve a target data retention time.

15. The device of claim 14 wherein the memory device includes a second array of charge storage elements and the programming control circuit is configured to implement a second controlled erase operation over a second predetermined period for such elements.

16. The device of claim 14 wherein the charge storage elements are electrically programmable memory cells.

17. The device of claim 14 wherein the memory device is embedded with other logic and I/O devices on the integrated circuit.

18. A memory device on an integrated circuit adapted with ephemeral data retention capability comprising:

an array of charge storage elements;

wherein said charge storage element is characterized by an inherent leakage current and is configurable;

to store a first amount of charge corresponding to a first unprogrammed state representing a first data value; and

to store a second amount of charge corresponding to a second programmed state representing a second data value;

a programming control circuit configured;

to set said array of charge elements to said second programmed state representing said second data value based on a first write operation;

to initiate and control an erase operation on said array, including at least a first mode in which a controlled erase charge is actively removed from selected charge storage elements at predetermined erase periods and in the absence of a new second write operation for such array;

to actively impose erase bias voltages to said array of charge storage elements during said controlled predetermined period so that said controlled erase charge is removed from such elements in addition to charge lost to leakage current by such elements; and

to cause apply the smallest possible bias required to remove charge from the selected charge storage elements during said controlled predetermined period to achieve a target data retention time.

19. The device of claim 18 wherein the memory device includes a second array of charge storage elements and the programming control circuit is configured to implement a second controlled erase operation over a second predetermined period for such elements.

20. The device of claim 18 wherein the charge storage elements are electrically programmable memory cells.

21. The device of claim 18 wherein the memory device is embedded with other logic and I/O devices on the integrated circuit.

22. A memory device on an integrated circuit adapted with ephemeral data retention capability comprising:

an array of charge storage elements;

wherein each charge storage element in said array is characterized by an inherent leakage current and is configurable;

to store a first amount of charge corresponding to a first state corresponding to a first state representing a first data value; and

to store a second amount of charge corresponding to a second state representing a second data value;

a programming control circuit configured;

to program said array of charge storage elements to said second data value based on a first write operation;

to initiate and control a slow erase operation on said array, including at least a first mode in which a controlled erase charge is actively removed from a selected charge storage element over a controlled predetermined period and in the absence of a new second write operation for such selected charge storage element;

wherein said programming control circuit is adapted to actively impose erase bias voltages to said array of charge storage elements during said controlled predetermined period so that said controlled erase charge is removed from such elements in addition to charge lost to leakage current by such elements, by applying the smallest possible bias required to remove charge from the selected charge storage elements during said controlled predetermined period to achieve a target data retention time;

further wherein a nominal data retention time capability of the selected charge storage elements is actively shortened by said slow erase operation.

23. The memory device of claim 22 wherein said controlled predetermined period ranges from 10⁴ to 10⁶ seconds.

24. The memory device of claim 22 wherein said array is partitioned into a plurality of subarrays of charge storage elements, and each of said plurality of subarrays is subjected to said slow erase operation at a different time in a predetermined program sequence.

25. The device of claim 22 wherein the programming control circuit is configured to cause holes to be injected into a floating gate of the selected charge storage elements.

26. The device of claim 22 wherein the selected charge storage elements are part of a secure storage area on the integrated circuit.

27. The device of claim 22 wherein the programming control circuit is configured to cause Fowler-Nordheim tunneling to remove said charge during said controlled predetermined period.

28. The device of claim 22 wherein the programming control circuit is configured to cause a negative erase voltage to be applied to a control gate of the selected charge storage elements and a positive voltage to a drain of said selected charge storage elements to remove said charge during said controlled predetermined period.

29. The device of claim 22 wherein a refresh operation is implemented by the programming control circuit with timing based on a target data retention characteristic of said charge storage element.

30. A memory device on an integrated circuit adapted with ephemeral data retention capability comprising:

an array of charge storage elements;

wherein said charge storage element is characterized by an inherent leakage current and is configurable;

to store a first amount of charge corresponding to a first unprogrammed state representing a first data value; and

to store a second amount of charge corresponding to a second programmed state representing a second data value;

a programming control circuit configured;

to set said array of charge elements to said second programmed state representing said second data value based on a first write operation;

to initiate and control an erase operation on said array, including at least a first mode in which a controlled erase charge is actively removed from selected charge storage elements at predetermined erase periods and in the absence of a new second write operation for such array;

wherein said programming control circuit is adapted to actively impose erase bias voltages to said array of charge storage elements during said controlled predetermined period so that said controlled erase charge is removed from such elements in addition to charge lost to leakage current by such elements;

further wherein a nominal data retention time capability of the selected charge storage elements is actively shortened by said slow erase operation.