Diode connected to a magnetic tunnel junction and self aligned with a metallic conductor and method of forming the same

• US 20010010938A1
• Filed: 03/20/2001
• Published: 08/02/2001
• Est. Priority Date: 08/31/1998
• Status: Active Grant

• Current Assignee: GlobalFoundries, Inc.
• Original Assignee: Gary Bela Bronner, Roy Edwin Scheuerlein, Stephen Mcconnell Gates
• Inventors: Bronner, Gary Bela, Gates, Stephen McConnell, Scheuerlein, Roy Edwin
• Granted Patent: US 6,562,634 B2
• Time in Patent Office: Days
• US Class Current: 438/3
• CPC Class Codes: B82Y 10/00 Nanotechnology for information processing, storage or transmission, e.g. quantum computing or single electron logic
• CPC Class Codes: H10B 61/10 comprising components having two electrodes, e.g. diodes or MIM elements

Abstract

A magneto-resistive memory cell and a method of forming the memory cell, includes a substrate, a single crystalline semiconductor diode formed in the substrate; and a first thin film conductor recessed in the substrate, and a second thin film conductor formed above a magnetic tunnel junction formed on the diode. The diode and the first thin film conductor share a non-planar common surface, such that the metal tunnel junction is a predetermined distance from the thin film conductor.

Claims

1. A magneto-resistive memory cell, comprising:

a substrate;

a single crystalline semiconductor diode formed in said substrate; and

a first thin film conductor recessed in said substrate; and

a second thin film conductor formed above a magnetic tunnel junction formed on said diode,

wherein said diode and said first thin film conductor share a non-planar common surface, such that a metal tunnel junction is a predetermined distance from said thin film conductor.

2. A nonvolatile memory cell structure, comprising:

a silicon substrate;

a diode formed in said substrate;

a first conductor located above said diode, and recessed in a trench formed in said substrate;

an insulator layer located above said first conductor;

a magnetic tunnel junction located above said insulator layer; and

a second conductor located above said magnetic tunnel junction.

3. The memory cell structure according to

claim 2

, wherein said first and second conductors comprise first and second thin film wires, respectively.

4. The memory cell according to

claim 2

, wherein an upper surface of said insulator layer comprises a planarized layer and is coplanar with a top surface of said silicon substrate.

5. A memory, comprising:

a magnetic tunnel junction;

a diode coupled to said magnetic tunnel junction and including first and second contacts; and

a metallic conductor coupled to said diode,

wherein a non-planar surface is shared by the metal conductor and a contact of said diode.

6. The memory according to

claim 5

, wherein the non-planar surface is one of recessed below and raised above a surface of the silicon substrate.

7. The memory according to

claim 5

, wherein said non-planar surface comprises a surface with a vertical extent.

8. The memory according to

claim 5

, wherein a plurality of diodes are connected to a plurality of magnetic tunnel junctions and said metallic conductor.

9. The memory according to

claim 8

, wherein said non-planar surface comprises a surface with a vertical extent shared by the metal conductor and a contact of each of said diodes.

10. The memory according to

claim 5

, wherein the shared surface includes a sloped surface and is recessed below the surface of a silicon wafer substrate.

11. The memory according to

claim 10

, wherein said sloped surface is sloped at an angle substantially between approximately 53 and approximately 57 degrees.

12. The memory according to

claim 11

wherein said sloped surface is sloped at an angle of substantially 55 degrees.

13. The memory according to

claim 5

, wherein the shared surface is the vertical edge of said metal conductor.

14. The memory according to

claim 13

, wherein said conductor comprises a patterned metallic conductor.

15. The memory according to

claim 5

, wherein the shared surface comprises a vertical edge etched into said silicon substrate.

16. The memory according to

claim 5

, wherein the shared surface comprises a vertical edge recessed into said silicon substrate.

17. A nonvolatile memory cell structure, comprising:

a crystal silicon wafer substrate;

an ion-implanted diode formed in said substrate;

a first thin film wire located above said diode, and recessed in a trench in said substrate;

an insulator layer located above said first thin film wire;

a magnetic tunnel junction located above said insulator layer; and

a second thin film wire located above said magnetic tunnel junction.

18. The memory cell according to

claim 17

, wherein an upper surface of said insulator layer comprises a planarized layer and is coplanar with a top surface of said silicon substrate.

19. The memory cell according to

claim 18

, wherein said planarized layer comprises a chemical mechanical polish (CMP) planarized layer.

20. A magnetic memory cell, comprising:

a magnetic tunnel junction;

a semiconductor single crystal silicon diode coupled to said magnetic tunnel junction in series; and

a metal thin film wire, positioned a predetermined distance from said magnetic tunnel junction for conducting a write current which changes the magnetic tunnel junction resistance sate, and addressing the memory cell.

21. The memory cell according to

claim 20

, wherein said diode is made in a crystal silicon substrate under the metal thin film wire, said metal thin film being an electrode of said diode, and being a conductor recessed in a trench in the silicon substrate,

wherein, above the thin film wire, are located a thin insulator layer and the MTJ, respectively, a thickness of the insulator defining the predetermined distance between the thin film wire and said magnetic tunnel junction.

22. The memory cell according to

claim 21

, wherein said conductor comprises a metal conductor, said trench being formed by a dry etching process in the silicon substrate.

23. The memory cell according to

claim 22

, wherein in a contact region, an n⁺ surface region is shallower than the insulator, such that there is no direct contact between the n⁺ surface region and the metal conductor.

24. The memory cell according to

claim 20

, wherein said predetermined distance is less than 0.04 μ

m.

25. A method for forming a memory cell, comprising:

depositing a silicon nitride layer onto a wafer substrate;

forming a trench in said substrate;

lining said trench with a layer of As-doped glass;

etching to remove the As-doped glass except in a cell location depositing a sacrificial oxide conformally over the entire wafer;

performing solid source diffusion including heating to diffuse As into the substrate;

stripping said sacrificial oxide and the As-doped glass;

lining the trenches with a conformal oxide trench liner;

lithographically patterning and forming a window at the cell location, said window being formed in the oxide trench liner on the bottom surface region of the trench, and removing said conformal oxide trench liner, thereby exposing the substrate;

forming an n-type region in the substrate at the window, and forming p-type region in the substrate at the window, said p-type region being relatively shallower than said n-type region;

filling said trench with first metal line conductor metal, and planarizing said first metal line conductor;

recessing said metal into the trench by selective reactive ion etching (RIE);

filling upper regions of the trench with an oxide; and

planarizing said oxide to the substrate surface.

26. The method according to

claim 25

, wherein said substrate comprises a silicon substrate, and said trenches are formed to have an approximately 1:

1.5 aspect ratio, and wherein a process of forming the conducting strap regions comprises;

lithographically defining a location of the strap, said lithographically defining determining a cell node on which a magnetic tunnel junction is formed;

removing the conformal oxide trench liner on one sidewall of the trench, and leaving the liner on an opposite sidewall;

reactive ion etching (RIE) both the oxide and the conformal oxide trench liner on one side only of the trench, thereby forming recessed regions in the oxide, the recessed region being located over the window;

depositing one of a metal and a doped polysilicon to fill the recessed regions, thereby forming the strap, said strap making ohmic contact to the n-type regions on the sidewall of the recessed regions;

planarizing said strap material to the surface of the substrate;

forming and patterning said magnetic tunnel junction, depositing an inter-layer dielectric (ILD), planarizing said ILD to the top surface of the magnetic tunnel junction, and forming second metal lines, said second metal lines comprising column lines, to form said memory cell.

27. The method according to

claim 25

, wherein said planarizing of said strap material comprises planarizing said strap material by chemical mechanical polishing (CMP).

28. A method of forming a memory, comprising:

providing a magnetic tunnel junction;

providing a diode coupled to said magnetic tunnel junction and including first and second contacts; and

coupling a metallic conductor to said diode, such that a non-planar surface is shared by the metal conductor and a contact of said diode.