Process for producing a semiconductor wafer with polished edge

• US 20010014570A1
• Filed: 01/30/2001
• Published: 08/16/2001
• Est. Priority Date: 02/03/2000
• Status: Abandoned Application

• Current Assignee: Wacker Siltronic Gesellschaft Fur Halbleitermaterialien AG
• Original Assignee: Wacker Siltronic Gesellschaft Fur Halbleitermaterialien AG
• Inventors: Altmann, Thomas, Winkler, Wolfgang, Heier, Gerhard, Wenski, Guido
• Application Number:
  US09/772,470
• Publication Number:
  US 20010014570A1
• Time in Patent Office: Days
• US Class Current: 451/41
• CPC Class Codes: B24B 37/08 for double side lapping
• CPC Class Codes: B24B 9/065 of thin, brittle parts, e.g. semiconductors, wafers
• CPC Class Codes: C30B 33/00 After-treatment of single crystals or homogeneous polycrystalline material with defined structure C30B31/00 takes precedence
• CPC Class Codes: H01L 21/02021 Edge treatment, chamfering
• CPC Class Codes: H01L 21/02024 Mirror polishing

Abstract

There is a process for producing a semiconductor wafer having a front surface and a back surface and a polished edge, in which the semiconductor wafer is subjected to polishing on both sides. The process includes the following temporal sequence of steps: (a) polishing of the edge of the semiconductor wafer using a polishing cloth, with an alkaline polishing abrasive being supplied continuously; (b) simultaneous polishing of the front surface and the back surface of the semiconductor wafer, with an alkaline polishing abrasive being supplied continuously, between two rotating, lower and upper polishing plates which are both covered with a polishing cloth, both polishing cloths substantially comprising a porous, homogeneous, fiber-free polymer foam, and the polishing cloth of the lower polishing plate having a smooth surface and the polishing cloth of the upper polishing plate having a surface which is interrupted by channels; immediately followed by: (c) complete wetting of the front surface and the back surface and the edge of the semiconductor wafer with a film of liquid; and (d) cleaning and drying of the semiconductor wafer. There is also a semiconductor wafer which has been polished on both sides, having a front surface and a back surface and a polished edge and a maximum local flatness value SFQR_max of less than or equal to 0.13 μm, based on partial regions of a surface grid on the front surface of the semiconductor wafer, which has been produced in accordance with this method.

Claims

1. A process for producing a semiconductor wafer having a front surface and a back surface and a polished edge, between said front and back surface, in which the semiconductor wafer is subjected to polishing on both sides, which comprises the following temporal sequence of steps:

(a) polishing of the edge of the semiconductor wafer using a polishing cloth, with an alkaline polishing abrasive being supplied continuously;

(b) simultaneous polishing of the front surface and the back surface of the semiconductor wafer, with an alkaline polishing abrasive being supplied continuously, between two rotating, lower and upper polishing plates which are both covered with a polishing cloth, both polishing cloths substantially comprising a porous, homogeneous, fiber-free polymer foam, and the polishing cloth of the lower polishing plate having a smooth surface and the polishing cloth of the upper polishing plate having a surface which is interrupted by channels;

immediately followed by;

(c) complete wetting of the front surface and the back surface and the edge of the semiconductor wafer with a film of liquid; and

(d) cleaning and drying of the semiconductor wafer.

2. The process as claimed in

claim 1

, comprising

resting semiconductor wafer in a cutout in a carrier during steps (b) and (c).

3. The process as claimed in

claim 2

,

wherein the carrier has a thickness which is 2 to 20 μ

m less than a thickness of a fully polished semiconductor wafer.

4. The process as claimed in

claim 1

,

wherein step (b) reduces thickness of the semiconductor wafer by 2 to 100 μ

m.

5. The process as claimed in

claim 1

,

wherein the alkaline polishing abrasive used in step (a) and step (b) substantially comprises a suspension of silicon dioxide particles and a base selected from the group consisting of an inorganic base and an organic base and a mixture thereof in ultrapure water, which is at a pH of from 9 to 12.

6. The process as claimed in

claim 1

,

wherein the polishing cloths of the lower and upper polishing plate substantially comprise polyurethane and have a Shore A hardness of from 60 to 90.

7. The process as claimed in

claim 1

,

wherein the polishing cloth of the upper polishing plate has a regular arrangement of channels, resembling a chessboard, with a square size of from 5 mm=5 mm to 50 mm=50 mm and a channel width and depth of from 0.5 mm to 2 mm.

8. The process as claimed in

claim 1

,

wherein the film of liquid generated in step (c) is completely removed in the subsequent cleaning step (d).

9. The process as claimed in

claim 1

,

wherein the film of liquid generated in step (c) contains a compound selected from the group consisting of polyhydric alcohols, polyalcohols, surfactants, and a mixture thereof.

10. The process as claimed in

claim 9

,

wherein the film of liquid contains glycerol.

11. The process as claimed in

claim 9

,

wherein the film of liquid comprises a compound selected from the group consisting of polyether polyol, polyvinyl alcohol and a mixture thereof.

12. The process as claimed in

claim 9

,

wherein the film of liquid contains a surfactant, and said film of liquid is generated by feeding the semiconductor wafer initially with a mixture of aqueous polishing abrasive and the surfactant and then, for a brief period, feeding with ultrapure water.

13. The process as claimed in

claim 1

, comprising

removing the semiconductor wafer, after step (c), from a polishing machine with a vacuum nozzle holder.

14. The process as claimed in

claim 1

,

wherein, after steps (a) to (d) have been carried out, applying a semiconductive, epitaxial coating to the front surface of the semiconductor wafer.

15. The process as claimed in

claim 1

,

wherein, after steps (a) to (d) have been carried out, final polishing is carried out on the front surface of the semiconductor wafer;

and the semiconductor wafer is cleaned and dried; and

a semiconductive, epitaxial coating is applied to the front surface of the semiconductor wafer.

16. A semiconductor wafer which has been polished on both sides, having a front surface and a back surface and a polished edge between said front and back surface and a maximum local flatness value SFQR_max of less than or equal to 0.13 μ

m, based on partial regions of a surface grid on the front surface of the semiconductor wafer, which has been produced according to the process of

claim 1

.