Semiconductor device and method of manufacturing the same

• US 20010015463A1
• Filed: 01/04/2001
• Published: 08/23/2001
• Est. Priority Date: 01/21/2000
• Status: Active Grant

• Current Assignee: Godo Kaisha IP Bridge 1 (IP Bridge, Inc.)
• Original Assignee: NEC Corporation
• Inventors: Wakabayashi, Hitoshi, Saito, Yukishige
• Granted Patent: US 6,483,151 B2
• Time in Patent Office: Days
• US Class Current: 257/371
• CPC Class Codes: H01L 21/28088 the final conductor layer next to the insulator being a composite, e.g. TiN
• CPC Class Codes: H01L 21/823842 gate conductors with different gate conductor materials or different gate conductor implants, e.g. dual gate structures
• CPC Class Codes: H01L 21/823857 with a particular manufacturing method of the gate insulating layers, e.g. different gate insulating layer thicknesses, particular gate insulator materials or particular gate insulator implants
• CPC Class Codes: H01L 29/4966 the conductor material next to the insulator being a composite material, e.g. organic material, TiN, MoSi2 H01L29/4908, H01L29/4983 take precedence
• CPC Class Codes: H01L 29/66545 using a dummy, i.e. replacement gate in a process wherein at least a part of the final gate is self aligned to the dummy gate
• CPC Class Codes: H01L 29/6656 using multiple spacer layers, e.g. multiple sidewall spacers
• CPC Class Codes: H01L 29/6659 with both lightly doped source and drain extensions and source and drain self-aligned to the sides of the gate, e.g. lightly doped drain [LDD] MOSFET, double diffused drain [DDD] MOSFET
• CPC Class Codes: H01L 29/66606 with final source and drain contacts formation strictly before final or dummy gate formation, e.g. contact first technology H01L29/66621 takes precedence
• CPC Class Codes: H01L 29/7833 with lightly doped drain or source extension, e.g. LDD MOSFET's; DDD MOSFET's for thin film transistors H01L29/78618
• CPC Class Codes: Y10S 257/915 with titanium nitride portion or region

Abstract

One object of the present invention is to suppress a threshold voltage of at least an n-channel MISFET using a nitride of a high melting point metal at it'"'"'s gate electrode. In order to achieve the object, a gate electrode 109 of a p-channel MISFET is constituted of a titanium nitride film 106 and a tungsten film 107 formed on the film 106 and a gate electrode 110a of an n-channel MISFET is constituted of a titanium nitride film 106a and a tungsten film 107 formed on the film 106a. The titanium nitride film 106a is formed by nitrogen ion implantation in the titanium nitride film 106 to decrease the work function.

Claims

1. A semiconductor device comprising:

a silicon substrate;

an n-type well and a p-type well formed on the surface of said silicon substrate and separated from each other by an element separation region;

a p-channel type insulated gate field effect transistor formed on said n-type well and having a first gate electrode; and

an n-channel type insulated gate field effect transistor formed on said p-type well and having a second gate electrode;

said first gate electrode formed on the surface of said n-type well by interposing a first gate oxide film ,and including a first conductive film of a nitride of a first high melting point metal directly contacted to the surface of said first gate oxide film and a second high melting point metal film formed on the surface of said first conductive film, and

said second gate electrode formed on the surface of said p-well by interposing a second gate oxide film , and including a second conductive film of a nitride of said first high melting point metal with higher nitrogen content than that of said first conductive film and directly contacted to the surface of said second gate oxide film and a metal film formed on the surface of said second conductive film.

2. A semiconductor device as set forth in

claim 1

, wherein side faces of said first and second gate electrodes are respectively directly coated with side wall spacers,

said first and second gate oxide films are made of thermal oxidation films, said metal film constituting said second gate electrode is made of said second high melting point metal film and

said first high melting point metal is selected from titanium, tungsten, and tantalum.

3. A semiconductor device as set forth in

claim 1

, wherein each side face of said first gate electrode is directly coated with a side wall spacer,

each side face of said second gate electrode is coated

with a side wall spacer through said second gate oxide film and

said first high melting point metal is selected from titanium, tungsten, and tantalum.

4. A semiconductor device as set forth in

claim 3

, wherein crystal orientation of said second conductive film differs from that of said first conductive film.

5. A semiconductor device comprising:

a silicon substrate;

an n-type well and a p-type well formed on the surface of said silicon substrate and separated from each other by an element separation region;

a p-channel type insulated gate field effect transistor formed on said n-type well and having a first gate electrode;

an n-channel type insulated gate field effect transistor formed on said p-type well and having a second gate electrode; and

side wall spacers respectively made of insulating films coating the side faces of said first and second gate electrodes, wherein

said first gate electrode formed on the surface of said n-type well by interposing a first gate oxide film formed by thermal oxidation is constituted of a first conductive film of a nitride of a first high melting point metal directly coating the surface of said gate oxide film and a second high melting point metal film formed on the surface of said first conductive film,

said second gate electrode formed on the surface of said p-well by interposing a gate insulating film containing nitrogen is constituted of a second conductive film of a nitride of said first high melting point metal with a higher nitrogen content than that of said first conductive film and directly coating the surface of said gate insulating film and a metal film formed on the surface of said second conductive film,

side faces of said first gate electrode are directly coated with said side wall spacers and

side faces of said second gate electrode are coated with said side wall spacers through said gate insulating film.

6. A semiconductor device as set forth in claim5, wherein said gate insulating film is a silicon nitride film or a silicon nitride oxide film, and

said first high melting point metal is selected from titanium, tungsten, and tantalum.

7. A semiconductor device comprising:

a silicon substrate;

an n-type well and a p-type well formed on the surface of said silicon substrate and separated from each other by an element separation region;

a p-channel type insulated gate field effect transistor formed on said n-type well and having a first gate electrode;

an n-channel type insulated gate field effect transistor formed on said p-type well and having a second gate electrode; and

side wall spacers respectively made of insulating films coating the side faces of said first and second gate electrodes, wherein

said first gate electrode formed on the surface of said n-type well by interposing a first gate oxide film formed by thermal oxidation is constituted of a first conductive film of a nitride of a first high melting point metal directly coating the surface of said gate oxide film and a second high melting point metal film formed on the surface of said first conductive film,

said second gate electrode formed on the surface of said p-well by interposing a gate insulating film is constituted of a second conductive film of a nitride of a third high melting point metal different from the first high melting point metal and directly coating the surface of said gate insulating film and a metal film formed on the surface of said second conductive film,

side faces of said first gate electrode are directly coated with said side wall spacers and

side faces of said second gate electrode are coated with said side wall spacers through said gate insulating film.

8. A semiconductor device as set forth in

claim 7

, wherein said first high melting point metal is titanium and said third high melting point metal is tantalum.

9. A method of manufacturing a semiconductor device comprising the steps of:

forming an n-type well and a p-type well separated from each other by an element separation region on the surface of a silicon substrate and forming a first gate oxide film on the surface of said n-type well and p-type well by thermal oxidation;

forming a conductive film of a nitride of a first high melting point metal on the whole surface,

forming a mask film pattern covering said n-type well surface,

ion-implanting nitrogen in said conductive film by using said mask film pattern as a mask;

successively forming a second high melting point metal film and a hard mask film of a first insulating film on the whole surface of said silicon substrate; and

patterning said hard mask film, said second high melting point metal film and said conductive film in sequence by anisotropic etching to form a first and a second gate electrodes on said n-type well and p-type well, respectively.

10. A method of manufacturing a semiconductor device as set forth in

claim 9

, wherein said first high melting point metal is selected from titanium, tungsten, and tantalum.

11. A method of manufacturing a semiconductor device comprising the steps of:

forming an n-type well and a p-type well separated from each other by an element separation region on the surface of a silicon substrate and forming a first gate oxide film on the surface of said n-type well and p-type well by thermal oxidation;

forming a first conductive film of a nitride of a first high melting point metal on the whole surface of said silicon substrate by reactive sputtering at a first nitrogen gas flow rate and further forming a second high melting point metal film and hard mask film of a first insulating film;

patterning said hard mask film, said second high melting point metal film and said first conductive film in sequence by anisotropic etching to form a first gate electrode on the surface of said n-type well and at the same time to form a temporary gate electrode structure on said p-type well;

forming an interlayer insulating film on the whole surface and performing chemical-mechanical polishing to said interlayer insulating film until the upper face of said hard mask film is exposed;

forming a mask film pattern covering said n-type well and successively removing said hard mask film, said temporary gate electrode structure and said first gate oxide film by etching using said mask film pattern as a mask;

forming a second gate oxide film on the whole surface;

forming a second conductive film of a nitride film of a first high melting point metal by reactive sputtering at a second nitrogen gas flow rate higher than said first nitrogen gas flow rate and further forming a metal film on the whole surface; and

forming a second gate electrode on the surface of said p-type well by carrying out chemical-mechanical polishing of said metal film, second conductive film and second gate oxide film until the upper face of said interlayer insulating film is exposed.

12. A method of manufacturing a semiconductor device as set forth in

claim 11

, wherein said second nitrogen gas flow rate is so set as to make the crystal orientation of said second conductive film different from the crystal orientation of said first conductive film.

13. A method of manufacturing a semiconductor device as set forth in either one of claims 11 and 12, wherein said first high melting point metal is selected from titanium, tungsten, and tantalum.

14. A method of manufacturing a semiconductor device comprising the steps of:

forming an n-type well and a p-type well separated from each other by an element separation region on the surface of a silicon substrate and forming a gate oxide film on the surface of said n-type well and p-type well by thermal oxidation;

forming a first conductive film of a nitride film of a first high melting point metal on the whole surface and further successively forming a second high melting point metal film and hard mask film of a first insulating film;

successively patterning said hard mask film, said second high melting point metal film and said conductive film by anisotropic etching to form a first gate electrode on the surface of said n-type well and at the same time to form a temporary gate electrode structure on said p-type well;

forming a second insulating film on the whole surface;

forming side wall spacers respectively coating the side faces of said first and temporary gate electrodes by etching back said second insulating film;

forming a p⁺-type source/drain region on the surface of said n-type well by ion implantation of p-type impurities using said first gate electrode and side wall spacers as a mask;

forming an n⁺-type source/drain region on the surface of said p-type well by ion implantation of n-type impurities using said temporary gate electrode structure and side wall spacers as a mask;

forming a third high melting point metal film on the whole surface;

forming a high melting point metal silicide layer in a self-alignment manner on the surface of said p⁺-type source/drain region and n⁺-type source/drain region;

forming an interlayer insulating film on the whole surface and carrying out chemical-mechanical polishing of said interlayer insulating film until the upper face of said hard mask film is exposed;

forming a mask film pattern covering of said n-type well and successively removing said hard mask film, said temporary gate electrode structure and said gate oxide film by etching using said mask film pattern as a mask;

forming a gate insulating film containing nitrogen on the whole surface by a chemical vapor deposition method;

successively forming a second conductive film of a nitride film of a first high melting point metal and a metal film on the whole surface;

diffusing nitrogen in said second conductive film from said gate insulating film by heating; and

carrying out chemical-mechanical polishing to said metal film, said second conductive film and said gate insulating film until the upper face of said interlayer insulating film is exposed and forming a second gate electrode on the surface of said p-type well.

15. A method of manufacturing a semiconductor device as set forth in

claim 14

, wherein said gate insulating film is a silicon nitride film or a silicon nitride oxide film and said first high melting point metal is selected from titanium, tungsten and tantalum.

16. A method of manufacturing a semiconductor device comprising the steps of:

forming an n-type well and a p-type well separated from each other by an element separation region on the surface of a silicon substrate and forming a gate oxide film on the surface of said n-type well and p-type well by thermal oxidation;

forming a first conductive film of a nitride film of a first high melting point metal on the whole surface and further successively forming a second high melting point metal film and hard mask film of a first insulating film;

successively patterning said hard mask film, said second high melting point metal film and said conductive film by anisotropic etching to form a first gate electrode on the surface of said n-type well and at the same time to form a temporary gate electrode structure on said p-type well;

forming a second insulating film on the whole surface;

forming side wall spacers respectively coating the side faces of said first and temporary gate electrodes by etching back said second insulating film;

forming a p⁺-type source/drain region on the surface of said n-type well by ion implantation of p-type impurities using said first gate electrode and side wall spacers as a mask, forming an n⁺-type source/drain region on the surface of said p-type well by ion implantation of n-type impurities using said temporary gate electrode structure and side wall spacers as a mask;

forming a third high melting point metal film on the whole surface and forming a high melting point metal silicide layer in a self-alignment manner on the surface of said p⁺-type source/drain region and n⁺-type source/drain region;

forming an interlayer insulating film on the whole surface and carrying out chemical -mechanical polishing to said interlayer insulating film until the upper face of said hard mask film is exposed;

forming a mask film pattern covering said n-type well and successively removing said hard mask film, said temporary gate electrode structure and said gate oxide film by etching using said mask film pattern as a mask;

forming a gate insulating film on the whole surface by a chemical vapor deposition method;

successively forming a second conductive film of a nitride film of a fourth high melting point metal and a metal film on the whole surface; and

forming a second gate electrode on the surface of said p-type well by carrying out chemical -mechanical polishing to said metal film, said second conductive film and said second gate oxide film until the upper face of said interlayer insulating film is exposed.

17. A method of manufacturing a semiconductor device as set forth in

claim 16

, wherein the first high melting point metal is titanium and said fourth high melting point metal is tantalum.