Systems and methods for computer initialization

• US 20010047473A1
• Filed: 02/02/2001
• Published: 11/29/2001
• Est. Priority Date: 02/03/2000
• Status: Abandoned Application

• Current Assignee: Realtime Data LLC (Realtime Data Compression Systems, Inc.)
• Original Assignee: Realtime Data LLC (Realtime Data Compression Systems, Inc.)
• Inventors: Fallon, James J.
• Application Number:
  US09/775,897
• Publication Number:
  US 20010047473A1
• Time in Patent Office: Days
• US Class Current: 713/2
• CPC Class Codes: G06F 1/24 Resetting means
• CPC Class Codes: G06F 3/0613 in relation to throughput
• CPC Class Codes: G06F 3/0638 Organizing or formatting or addressing of data
• CPC Class Codes: G06F 3/0658 Controller construction arrangements
• CPC Class Codes: G06F 3/0676 Magnetic disk device
• CPC Class Codes: G06F 9/4401 Bootstrapping security arrangements therefor G06F21/57
• CPC Class Codes: G06F 9/4406 Loading of operating system
• CPC Class Codes: G06F 9/4408 Boot device selection
• CPC Class Codes: G06F 9/445 Program loading or initiating bootstrapping G06F9/4401; security arrangements for program loading or initiating G06F21/57
• CPC Class Codes: H03M 7/30 Compression speech analysis-synthesis for redundancy reduction G10L19/00; for image communication H04N; Expansion; Suppression of unnecessary data, e.g. redundancy reduction

Abstract

Systems and methods for initializing devices such as computers, computer-based appliances, and processors and, in particular, systems and methods for initializing devices comprising one or more volatile logic devices after a power turn-on or a commanded reset. In one aspect, a method for initializing a computer system comprises sensing a command signal to boot the computer system, generating a first control signal to initialize a boot process, generating a second control signal to initialize a programmable logic device prior to completion of the initialization of the boot process, and booting the computer system using the initialized programmable logic device. In another aspect, a boot manager circuit is provided for managing initialization of a computer system. One embodiment of a boot manager circuit comprises a first sense circuit for sensing power-up and ensuring power stability, a second sense circuit for sensing a command signal to boot the computer system; a control circuit for generating a control signal in response to sensing of a command signal, to initialize a programmable logic device in advance of a boot process, and a state machine for outputting a flag indicative of the type of the type of boot process commanded.

Claims

1. A method for initializing a computer system, comprising the steps of:

sensing a command signal to boot the computer system;

generating a first control signal to initialize a boot process;

generating a second control signal to initialize a programmable logic device prior to completion of the initialization of the boot process; and

booting the computer system using the initialized programmable logic device.

2. The method of

claim 1

, wherein the second control signal causes the programmable logic device to self-load logic code from a memory device.

3. The method of

claim 1

, wherein the second control signal causes a logic device to load logic code into the programmable logic device.

4. The method of

claim 1

, further comprising the step of sensing power to ensure power stability prior to generating the second control signal.

5. The method of

claim 1

wherein the method steps are performed by a boot management circuit that manages the boot process.

6. The method of

claim 1

, further comprising the steps of generating a third control signal to indicate the type of boot process commanded.

7. The method of

claim 6

, wherein the type of boot process comprises one of a cold boot and a warm boot.

8. A program storage device readable by a machine, tangibly embodying a program of instructions executable by the machine to perform method steps for initializing a computer system, the method steps comprising:

sensing a command signal to boot the computer system;

generating a first control signal to initialize a boot process;

generating a second control signal to initialize a programmable logic device prior to completion of the initialization of the boot process; and

booting the computer system using the initialized programmable logic device.

9. The program storage device of

claim 8

, wherein the second control signal causes the programmable logic device to self-load logic code from a memory device.

10. The program storage device of

claim 8

, wherein the second control signal causes a logic device to load logic code into the programmable logic device.

11. The program storage device of

claim 8

, further comprising instructions for sensing power to ensure power stability prior to generating the second control signal.

12. The program storage device of

claim 8

, further comprising instructions for generating a third control signal to indicate the type of boot process commanded.

13. The program storage device of

claim 12

, wherein the type of boot process comprises one of a cold boot and a warm boot.

14. A circuit for managing initialization of a computer system, comprising:

a first sense circuit for sensing power-up and ensuring power stability;

a second sense circuit for sensing a command signal to boot the computer system;

a control circuit for generating a control signal in response to sensing of a command signal, to initialize a programmable logic device in advance of a boot process; and

a state machine for outputting a flag indicative of the type of the type of boot process commanded.

15. The circuit of

claim 14

, further comprising a first waveshaping circuit, operatively coupled to the first sense circuit, for generating a first pulse signal that is utilized to generate the control signal in response to a cold boot command.

16. The circuit of

claim 15

, wherein the first waveshaping circuit comprises a falling edge differentiator circuit.

17. The circuit of

claim 14

, further comprising a second waveshaping circuit, operatively coupled to the second sense circuit, for generating a second pulse signal that is utilized to generate the control signal in response to a warn boot command.

18. The circuit of

claim 17

, wherein the second waveshaping circuit comprises a rising edge differentiator circuit.

19. A system for initializing a computer, comprising:

a boot storage device for storing initialization program code for initializing a computer during a boot process; and

a boot device adapter, operatively interfaced with the boot storage device, for accessing the initialization program code from the boot storage device in response to a request from the computer system;

wherein the boot device adapter comprises;

a programmable logic device; and

a boot control circuit for generating a control signal to initialize the programmable logic device in advance of the boot process.

20. The system of

claim 19

, further comprising a memory device for storing logic code associated with the programmable logic device.

21. The system of

claim 20

, wherein the memory device resides in one of the boot device adapter, the computer system and both.

22. The system of

claim 20

, wherein the programmable logic device self-loads the logic code from the memory device in response to the control signal.

23. The system of

claim 22

, wherein the logic code comprises non-volatile logic code residing in memory on the boot storage device.

24. The system of

claim 19

, further comprising a digital signal processor (DSP) that initializes the programmable logic device in response to the control signal.

25. The system of

claim 24

, wherein the boot control circuit comprises a state machine that outputs a flag signal indicative of the type of boot process commanded.

26. The system of

claim 24

, wherein the DSP processes the flag signal to determine whether to re-initialize the programmable logic device, if the flag signal indicates a warm boot process.

27. The system of

claim 24

, wherein the DSP resides on the boot device adapter.

28. The system of

claim 24

, wherein the DSP is operatively connected to the programmable logic device through a dedicated bus of the DSP.

29. The system of

claim 28

, wherein the dedicated bus comprises a communications port.

30. The system of

claim 24

, wherein the DSP retrieves logic code associated with the programmable logic device from a memory device residing on the boot device adapter.

31. The system of

claim 30

, wherein the memory device stores logic code associated with the DSP.