Mosfet with strained channel layer

• US 20020008289A1
• Filed: 07/20/2001
• Published: 01/24/2002
• Est. Priority Date: 07/24/2000
• Status: Abandoned Application

• Current Assignee: President of Tohoku University
• Original Assignee: President of Tohoku University
• Inventors: Tsuchiya, Toshiaki, Matsuura, Takashi, Murota, Junichi, Sakuraba, Masao
• Application Number:
  US09/908,574
• Publication Number:
  US 20020008289A1
• Time in Patent Office: Days
• US Class Current: 257/369
• CPC Class Codes: H01L 21/8238 Complementary field-effect transistors, e.g. CMOS
• CPC Class Codes: H01L 27/092 complementary MIS field-effect transistors
• CPC Class Codes: H01L 29/802 with heterojunction gate, e.g. transistors with semiconductor layer acting as gate insulating layer, MIS-like transistors H01L29/806 takes precedence; with one dimensional electron gas H01L29/775; with dimensional electron gas H01L29/778

Abstract

A semiconductor device is disclosed which allows for ease of fabrication of CMOS LSI chips and is adapted to increase the mobility of electrons and holes. The semiconductor device comprises a substrate, an insulating layer formed over the substrate, and a stacked Si/SiGe/Si region comprising a first layer of Si, a layer of SiGe, and a second layer of Si which are sequentially formed in this order on the insulating layer. The topmost second layer of Si and the layer of SiGe are strained due to the difference in lattice constant between each layer in the stacked Si/SiGe/Si region. An n-MOSFET and a p-MOSFET are formed in the stacked region. The n-MOSFET has a surface channel consisting of the second Si layer, whereas the p-MOSFET has a double channel of a buried channel consisting of the SiGe layer and a surface channel consisting of the second Si layer.

Claims

1. A semiconductor device comprising:

a substrate;

an insulating layer formed over the substrate;

a stacked Si/SiGe/Si region in which a first layer of Si, a layer of SiGe and a second layer of Si are sequentially formed on the insulating layer, the topmost second layer of Si and the layer of SiGe being strained based on the difference in lattice constant between each layer in the stacked Si/SiGe/Si region; and

an n-MOSFET and a p-MOSFET formed in the stacked Si/SiGe/Si region, the n-MOSFET having a surface channel consisting of the second strained layer of Si, and the p-MOSFET having a double channel of a buried channel consisting of the strained layer of SiGe and a surface channel consisting of the second strained layer of Si.

2. The semiconductor device according to claim 1, wherein each of the layer of SiGe and the second layer of Si is formed by means of chemical vapor deposition.

3. The semiconductor device according to claim 2, wherein the layer of SiGe contains carbon atoms.

4. The semiconductor device according to claim 1, wherein the substrate is an Si monocrystalline substrate.