Packet processing device

• US 20020016905A1
• Filed: 02/23/2001
• Published: 02/07/2002
• Est. Priority Date: 08/02/2000
• Status: Active Grant

• Current Assignee: Fujitsu Limited
• Original Assignee: Fujitsu Limited
• Inventors: Tsuruoka, Tetsumei, Kojima, Yuji, Umezaki, Yasuyuki, Shimozono, Yoshitomo
• Granted Patent: US 7,089,407 B2
• Time in Patent Office: Days
• US Class Current: 712/36
• CPC Class Codes: H04L 45/00 Routing or path finding of packets in data switching networks routing or path finding in wireless networks H04W40/00
• CPC Class Codes: H04L 45/60 Router architectures

Abstract

The packet processing device which can reserve a calculation time for each instruction procedure execution unit independent of the data length of a packet by sequentially selecting an instruction procedure execution unit by a selection signal generation unit and performing a calculation on each packet when packets are consecutively input to a packet access unit is disclosed.

Claims

1. A packet processing device having a packet processor for performing a predetermined packet process by executing an instruction, said packet processor comprising:

a packet access unit comprising a plurality of first registers, shifting received packet data among said first registers sequentially from the beginning to transmit the shifted packet data;

a plurality of instruction procedure execution units for performing in parallel a predetermined calculation corresponding to each of a plurality of packets according to the packet data held in said first registers in said packet access unit; and

a selection signal generation unit for generating a selection signal for selecting said instruction procedure execution unit for performing the calculation corresponding to each of the packets in synchronization with a timing of receiving each packet.

2. The packet processing device according to claim 1, said packet processor further comprising:

an intermediate data transfer unit comprising a plurality of second registers, shifting intermediate data obtained as a process result from said instruction procedure execution unit corresponding to the packet data among said second registers to transfer the shifted intermediate data in synchronization with the shifting of the packet data using said first registers in said packet access unit.

3. The packet processing device according to claim 1, wherein

said packet access unit comprises:

a first selector for selectively fetching the packet data held in said plurality of first registers, and inputting the data to said instruction procedure execution unit; and

a second selector for inputting resultant data obtained by said instruction procedure execution unit executing a specified instruction procedure to said first register corresponding to an execution order of the instruction procedure.

4. The packet processing device according to claim 2, wherein

said intermediate data transfer unit comprises:

a third selector for selectively fetching the intermediate data held in said plurality of second registers, and inputting the data to said instruction procedure execution unit; and

a fourth selector for inputting the intermediate data obtained by said instruction procedure execution unit executing a specified instruction procedure to said second register corresponding to an execution order of the instruction procedure.

5. The packet processing device according to claim 1, wherein

each of said plurality of instruction procedure execution units comprises:

a control unit for sequentially decoding a plurality of instruction procedures;

an arithmetic unit for performing a predetermined calculation process corresponding to a result of the decoding by said control unit; and

a general-purpose register group comprising a plurality of general-purpose registers functioning as work areas for said arithmetic unit, and

a number of the plurality of the instruction procedures prepared for performing a process corresponding to each of the packets is set to a value corresponding to a time longer than a shortest reception interval between two of the packets.

6. The packet processing device according to claim 1, further comprising for at least one of said first and second registers

a write location setting unit for variably setting a location at which externally input data is to be written.

7. The packet processing device according to claim 1, further comprising for at least one of said first and second registers

a read location setting unit for variably setting a location at which externally output data is to be read.

8. The packet processing device according to claim 1, comprising a plurality of serially connected packet processors.