Packet processing device processing input packet data in a packet routing device

• US 7,089,407 B2
• Filed: 02/23/2001
• Issued: 08/08/2006
• Est. Priority Date: 08/02/2000
• Status: Expired due to Fees

• Current Assignee: Fujitsu Limited
• Original Assignee: Fujitsu Limited
• Inventors: Umezaki, Yasuyuki, Shimozono, Yoshitomo, Tsuruoka, Tetsumei, Kojima, Yuji
• Primary Examiner(s): Pan, Daniel H.
• Application Number:
  US09/792,304
• Publication Number:
  US 20020016905A1
• Time in Patent Office: 1,992 Days
• Field of Search: 712/8, 712/11, 712/25, 712/225
• US Class Current: 712/225
• CPC Class Codes: H04L 45/00 Routing or path finding of packets in data switching networks routing or path finding in wireless networks H04W40/00
• CPC Class Codes: H04L 45/60 Router architectures

Abstract

A packet processing device which can reserve a calculation time for each instruction procedure execution unit independent of the data length of a packet by sequentially selecting an instruction procedure execution unit by a selection signal generation unit and performing a calculation on each packet when packets are consecutively input to a packet access unit is disclosed.

Claims

1. A packet processing device having a packet processor for performing a predetermined packet process by executing an instruction, said packet processor comprising:

a packet access unit comprising a plurality of first registers, moving received packet data into said first registers sequentially from the beginning and moving the moved packet data among said first registers and transmitting the moved packet data;

a plurality of instruction procedure execution units, every instruction procedure execution unit having the same configuration as each other, for performing in parallel a predetermined calculation corresponding to each of a plurality of packets according to the packet data held in said first registers in said packet access unit;

a selection signal generation unit for generating a selection signal for selecting one of said instruction procedure execution units for performing the calculation corresponding to each of the packets in synchronization with a timing of receiving each packet; and

an intermediate data transfer unit comprising a plurality of second registers, moving intermediate data obtained as a process result from one of said instruction procedure execution units corresponding to the packet data into said second registers to transfer the moved intermediate data in synchronization with the moving of the packet data and in parallel using said first registers in said packet access unit.

2. The packet processing device according to claim 1, wherein

said intermediate data transfer unit comprises:

a third selector for executing an operation in parallel for each of said plurality of instruction procedure execution units that selectively fetch the intermediate data held in one or more of said plurality of second registers, and inputting the data to one of said plurality of instruction procedure execution units; and

a fourth selector for executing an operation in parallel for each of said plurality of instruction procedure execution units that inputs the intermediate data obtained by one of said plurality of instruction procedure execution units executing a specified instruction procedure to one of said plurality of second registers corresponding to an execution order of the instruction procedure.

3. The packet processing device according to claim 1, said second registers further comprising:

a write location setting unit for variably setting a location at which externally input data is to be written.

4. The packet processing device according to claim 1, said second registers further comprising:

a read location setting unit for variably setting a location at which externally output data is to be read.

5. A packet processing device having a packet processor for performing a predetermined packet process by executing an instruction, said packet processor comprising:

a packet access unit comprising a plurality of first registers, moving received packet data into said first registers sequentially from the beginning and moving the moved packet data among said first registers and transmitting the moved packet data;

a plurality of instruction procedure execution units, every instruction procedure execution unit having the same configuration as each other, for performing in parallel a predetermined calculation corresponding to each of a plurality of packets according to the packet data held in said first registers in said packet access unit; and

a selection signal generation unit for generating a selection signal for selecting one of said instruction procedure execution units for performing the calculation corresponding to each of the packets in synchronization with a timing of receiving each packet,

wherein said packet access unit comprises;

a first selector for executing an operation in parallel for each of said plurality of instruction procedure execution units that selectively fetch the packet data held in one or more of said plurality of first registers, and inputting the data to one of said plurality of instruction procedure execution units; and

a second selector for executing an operation in parallel for each of said plurality of instruction procedure execution units that inputs resultant data obtained by one of said plurality of instruction procedure execution units executing a specified instruction procedure to one of said plurality of first registers corresponding to an execution order of the instruction procedure.

6. The packet processing device according to claim 5, said first registers further comprising:

a write location setting unit for variably setting a location at which externally input data is to be written.

7. The packet processing device according to claim 5, said first registers further comprising:

a read location setting unit for variably setting a location at which externally output data is to be read.

8. The packet processing device according to claim 5, including a plurality of serially connected packet processors.

9. A packet processing device having a packet processor for performing a predetermined packet process by executing an instruction, said packet processor comprising:

a packet access unit comprising a plurality of first registers, moving received packet data into said first registers sequentially from the beginning and moving the moved packet data among said first registers and transmitting the moved packet data;

a plurality of instruction procedure execution units, every instruction procedure execution unit having the same configuration as each other, for performing in parallel a predetermined calculation corresponding to each of a plurality of packets according to the packet data held in said first registers in said packet access unit; and

a selection signal generation unit for generating a selection signal for selecting one of said instruction procedure execution units for performing the calculation corresponding to each of the packets in synchronization with a timing of receiving each packet,

wherein

each of said plurality of instruction procedure execution units comprises;

a control unit for sequentially decoding a plurality of instruction procedures;

an arithmetic unit for performing a predetermined calculation process corresponding to a result of the decoding by said control unit; and

a general-purpose register group comprising a plurality of general-purpose registers functioning as work areas for said arithmetic unit, and

a number of the plurality of the instruction procedures prepared for performing a process corresponding to each of the packets is set to a value corresponding to a time longer than a shortest reception interval between two of the packets.

10. The packet processing device according to claim 9, said first registers further comprising:

a write location setting unit for variably setting a location at which externally input data is to be written.

11. The packet processing device according to claim 9, said first registers further comprising:

a read location setting unit for variably setting a location at which externally output data is to be read.

12. The packet processing device according to claim 9, including a plurality of serially connected packet processors.

13. A packet processing device having a packet processor for performing a predetermined packet process by executing an instruction, said packet processor comprising:

a packet access unit comprising a plurality of first registers, moving received packet data including a packet header into said first registers sequentially from the beginning and moving the moved packet data among said first registers and transmitting the moved packet data;

a plurality of instruction procedure execution units, every instruction procedure execution unit having the same configuration as each other, for performing in parallel a predetermined calculation corresponding to each of a plurality of packets according to the packet data held in said first registers in said packet access unit; and

a selection signal generation unit for generating a selection signal for selecting one of said instruction procedure execution units for performing the calculation corresponding to each of the said packets in synchronization with a timing of receiving each packet,

wherein said packet access unit comprises;

a first selector for executing an operation in parallel for each of said plurality of instruction procedure execution units that selectively fetch the packet data held in one or more of said plurality of first registers, and inputting the data to one of said plurality of instruction procedure execution units; and

a second selector for executing an operation in parallel for each of said plurality of instruction procedure execution units that inputs resultant data obtained by one of said plurality of instruction procedure execution units executing a specified instruction procedure to one of said plurality of first registers corresponding to an execution order of the instruction procedure.

14. A packet processing device having a packet processor for performing a predetermined packet process by executing an instruction, said packet processor comprising:

a packet access unit comprising a plurality of first registers, moving, received packet data including a packet header into said first registers sequentially from the beginning and moving the moved packet data among said first registers and transmitting the moved packet data;

a plurality of instruction procedure execution units, every instruction procedure execution unit having the same configuration as each other, for performing in parallel a predetermined calculation corresponding to each of a plurality of packets according to the packet data held in said first registers in said packet access unit; and

a selection signal generation unit for generating a selection signal for selecting one of said instruction procedure execution units for performing the calculation corresponding to each of the said packets in synchronization with a timing of receiving each packet,

wherein each of said plurality of instruction procedure execution units comprises;

a control unit for sequentially decoding a plurality of instruction procedures;

an arithmetic unit for performing a predetermined calculation process corresponding to a result of the decoding by said control unit; and

a general-purpose register group comprising a plurality of general-purpose registers functioning as work areas for said arithmetic unit, and

a number of the plurality of the instruction procedures prepared for performing a process corresponding to each of the packets is set to a value corresponding to a time longer than a shortest reception interval between two of the packets.