INTEGRATED CIRCUITS AND METHODS FOR THEIR FABRICATION

• US 20020063311A1
• Filed: 12/17/1999
• Published: 05/30/2002
• Est. Priority Date: 10/29/1996
• Status: Active Grant

• Current Assignee: Invensas Corporation
• Original Assignee: Oleg Siniaguine
• Inventors: SINIAGUINE, OLEG
• Granted Patent: US 6,639,303 B2
• Time in Patent Office: Days
• US Class Current: 257/621
• CPC Class Codes: H01L 21/304 Mechanical treatment, e.g. grinding, polishing, cutting H01L21/30625 takes precedence
• CPC Class Codes: H01L 21/3065 Plasma etching; Reactive-ion etching
• CPC Class Codes: H01L 21/441 Deposition of conductive or insulating materials for electrodes
• CPC Class Codes: H01L 21/76898 formed through a semiconductor substrate
• CPC Class Codes: H01L 2224/0401 Bonding areas specifically adapted for bump connectors, e.g. under bump metallisation [UBM]
• CPC Class Codes: H01L 2224/05552 in top view
• CPC Class Codes: H01L 2224/0557 the external layer being disposed on a via connection of the semiconductor or solid-state body
• CPC Class Codes: H01L 2224/05572 the external layer extending out of an opening
• CPC Class Codes: H01L 2224/13025 the bump connector being disposed on a via connection of the semiconductor or solid-state body
• CPC Class Codes: H01L 2225/06513 Bump or bump-like direct electrical connections between devices, e.g. flip-chip connection, solder bumps
• CPC Class Codes: H01L 2225/06541 Conductive via connections through the device, e.g. vertical interconnects, through silicon via [TSV] manufacturing via connections per se H01L21/76898
• CPC Class Codes: H01L 2225/06593 Mounting aids permanently on device; arrangements for alignment use of temporary supports H01L21/6835
• CPC Class Codes: H01L 23/481 Internal lead connections, e.g. via connections, feedthrough structures
• CPC Class Codes: H01L 23/482 consisting of lead-in layers inseparably applied to the semiconductor body electrodes H01L29/40
• CPC Class Codes: H01L 25/0657 Stacked arrangements of devices
• CPC Class Codes: H01L 25/50 Multistep manufacturing processes of assemblies consisting of devices, each device being of a type provided for in group H01L27/00 or H01L29/00 H01L21/50 takes precedence
• CPC Class Codes: H01L 29/0657 characterised by the shape of the body
• CPC Class Codes: H01L 2924/00012 Relevant to the scope of the group, the symbol of which is combined with the symbol of this group
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
• CPC Class Codes: H01L 2924/014 Solder alloys
• CPC Class Codes: H01L 2924/14 : Integrated circuits

Abstract

To fabricate back side contact pads that are suitable for use in a vertical integrated circuit, vias are made in the face side of a wafer, and dielectric and contact pad metal are deposited into the vias. Then the wafer back side is etched until the metal is exposed. When the etch exposes the insulator at the via bottoms, the insulator is etched slower than the wafer material (e.g. silicon). Therefore, when the dielectric is etched off and the metal is exposed, the dielectric protrudes down from the wafer back side around the exposed metal contact pads, by about 8 μm in some embodiments. The protruding dielectric portions improve insulation between the wafer and the contact pads when the contact pads are soldered to an underlying circuit. In some embodiments, before the contact pads are soldered, additional dielectric is grown on the wafer back side without covering the contact pads. In some embodiments, the wafer etch and the fabrication of the additional dielectric are performed one after another by a plasma process while the wafer is held in a non-contact wafer holder. In some embodiments, the wafer is diced and the dice are tested before the etch. The etch and the deposition of the additional dielectric are performed on good dice only. In some embodiments, the dice are not used for vertical integration.

Claims

1. A method for fabricating an integrated circuit, the method comprising:

providing a body having one or more openings in a first side;

fabricating a first dielectric and a conductor in each of the one or more openings with the conductor in each of the openings being separated from the body by the first dielectric;

removing material from a second side of the body to expose the conductor in each of the openings wherein the removing of the material comprises a process in which the removal rate of the first dielectric is lower than the removal rate of material of the body.

2. The method of claim 1 wherein in said process the removal rate of the first dielectric is about 10 times lower than the removal rate of the material of the body.

3. The method of claim 1 wherein in said process the removal rate of the first dielectric is higher than the removal rate of the conductor.

4. The method of claim 1 wherein the removal of the material from the second side of the body is followed by forming a second dielectric on the second side of the body but not on the conductor exposed on the second side.

5. The method of claim 1 wherein removing material from the second side comprises plasma etching of the second side of the body at about an atmospheric pressure as the body is held in a non-contact holder.

6. The method of claim 1 further comprising dicing the body before the removal of the material from the second side is completed, and

removing material from the second side comprises removing material from individual dice.

7. The method of claim 6 wherein removing material from the second side comprises:

removing material from the second side before the body is diced; and

removing material from individual dice after the body is diced.

8. The method of claim 6 wherein removing material from individual dice is preceded by testing of the dice of the body, and removing of the material from individual dice is performed only on a die or dice that have passed the test.

9. The method of claim 1 wherein the body comprises semiconductor material.

10. The method of claim 1 further comprising, after the removal of the material from the second side, connecting at least one integrated circuit of the body to one or more other integrated circuits to form a vertical integrated circuit, with at least one of the exposed conductors contacting a contact pad of another integrated circuit.

11. An integrated circuit comprising:

a semiconductor body having one or more circuit elements formed in or over a first side of the body;

one or more conductive contacts protruding from a second side of the body, wherein at least one contact is connected by one or more conductive lines to one or more circuit elements formed in or over the first side; and

a dielectric separating each contact from the body, wherein the dielectric adjacent each contact protrudes out of the semiconductor material of the second side around each contact.

12. The integrated circuit of claim 11 wherein the dielectric around each contact protrudes out of the semiconductor material of the second side by at least 8 μ

m measured in the direction perpendicular to the second side.

13. The integrated circuit of claim 11 further comprising dielectric that covers the second side of the circuit but exposes the contact.

14. The integrated circuit of claim 11 in combination with one or more other integrated circuits such that at least one of the contacts contacts a conductive contact on another integrated circuit, the combination forming a vertical integrated circuit.

16. The method of claim 15 wherein forming the dielectric layer on the second side of the body comprises exposing the second side to a plasma containing a species that reacts with the material of the body to form the dielectric layer but which does not form a dielectric on the one or more contacts.

18. The method of claim 17 wherein manufacturing of the individual integrated circuits comprises a back side etch of at least one of the individual circuits as the circuit is held in a non-contact holder.

20. The method of claim 19 wherein fabricating a plurality of integrated circuits comprises fabricating one or more circuit elements in or over a first side of the wafer, wherein each die has a first side which is part of the first side of the wafer;

and

wherein during the thinning process, the first side of each of the one or more dice faces the non-contact holder which protects one or more of the circuit elements fabricated in or over the first sides of the one or more dice from being etched.

21. The method of claim 19 wherein the etching process comprises a fluorine containing plasma etch at atmospheric pressure.

22. The method of claim 19 wherein the wafer comprises silicon.

23. The method of claim 19 wherein the thinning of the one or more dice is preceded by testing of the integrated circuits, and the thinning is performed only on a die or dice that have passed the test.

15. A method for fabricating an integrated circuit, the method comprising:

providing a body having one or more openings in a first side;

fabricating a first dielectric and a conductor in each of the one or more openings so that the conductor in each of the openings is separated from the body by the first dielectric;

removing material from a second side of the body to expose the conductor in each opening; and

forming a dielectric layer on the second side of the body by a process that does not form a dielectric layer on the one or more contacts.

17. A method for manufacturing a vertical integrated circuit, the method comprising:

manufacturing a plurality of individual integrated circuits;

after the manufacture of the individual integrated circuits has been completed, and each individual integrated circuit has been manufactured to its final thickness, attaching the individual integrated circuits to each other to form a vertical integrated circuit.

19. The method for integrated circuit fabrication, the method comprising:

fabricating a plurality of integrated circuits from a semiconductor wafer, wherein the wafer with the integrated circuits is thicker than the final thickness of each integrated circuit;

dicing the wafer into dice; and

thinning one or more dice obtained from the wafer as the one or more dice are held in a non-contact holder.