Integrated circuits and methods for their fabrication

• US 6,639,303 B2
• Filed: 12/17/1999
• Issued: 10/28/2003
• Est. Priority Date: 10/29/1996
• Status: Expired due to Term

• Current Assignee: Invensas Corporation
• Original Assignee: Tru-Si Technologies, Inc.
• Inventors: Siniaguine, Oleg
• Primary Examiner(s): Thomas, Tom
• Assistant Examiner(s): VU, HUNG K
• Application Number:
  US09/466,535
• Publication Number:
  US 20020063311A1
• Time in Patent Office: 1,411 Days
• Field of Search: 257/621, 257/698, 257/735, 257/777, 257/690, 257/699, 257/737, 257/780, 257/773, 257/774, 257/775, 438/667, 438/611, 438/461, 438/411
• US Class Current: 257/621
• CPC Class Codes: H01L 21/304 Mechanical treatment, e.g. grinding, polishing, cutting H01L21/30625 takes precedence
• CPC Class Codes: H01L 21/3065 Plasma etching; Reactive-ion etching
• CPC Class Codes: H01L 21/441 Deposition of conductive or insulating materials for electrodes
• CPC Class Codes: H01L 21/76898 formed through a semiconductor substrate
• CPC Class Codes: H01L 2224/0401 Bonding areas specifically adapted for bump connectors, e.g. under bump metallisation [UBM]
• CPC Class Codes: H01L 2224/05552 in top view
• CPC Class Codes: H01L 2224/0557 the external layer being disposed on a via connection of the semiconductor or solid-state body
• CPC Class Codes: H01L 2224/05572 the external layer extending out of an opening
• CPC Class Codes: H01L 2224/13025 the bump connector being disposed on a via connection of the semiconductor or solid-state body
• CPC Class Codes: H01L 2225/06513 Bump or bump-like direct electrical connections between devices, e.g. flip-chip connection, solder bumps
• CPC Class Codes: H01L 2225/06541 Conductive via connections through the device, e.g. vertical interconnects, through silicon via [TSV] manufacturing via connections per se H01L21/76898
• CPC Class Codes: H01L 2225/06593 Mounting aids permanently on device; arrangements for alignment use of temporary supports H01L21/6835
• CPC Class Codes: H01L 23/481 Internal lead connections, e.g. via connections, feedthrough structures
• CPC Class Codes: H01L 23/482 consisting of lead-in layers inseparably applied to the semiconductor body electrodes H01L29/40
• CPC Class Codes: H01L 25/0657 Stacked arrangements of devices
• CPC Class Codes: H01L 25/50 Multistep manufacturing processes of assemblies consisting of devices, each device being of a type provided for in group H01L27/00 or H01L29/00 H01L21/50 takes precedence
• CPC Class Codes: H01L 29/0657 characterised by the shape of the body
• CPC Class Codes: H01L 2924/00012 Relevant to the scope of the group, the symbol of which is combined with the symbol of this group
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
• CPC Class Codes: H01L 2924/014 Solder alloys
• CPC Class Codes: H01L 2924/14 : Integrated circuits

Abstract

To fabricate back side contact pads that are suitable for use in a vertical integrated circuit, vias are made in the face side of a wafer, and dielectric and contact pad metal are deposited into the vias. Then the wafer back side is etched until the metal is exposed. When the etch exposes the insulator at the via bottoms, the insulator is etched slower than the wafer material (e.g. silicon). Therefore, when the dielectric is etched off and the metal is exposed, the dielectric protrudes down from the wafer back side around the exposed metal contact pads, by about 8 μm in some embodiments. The protruding dielectric portions improve insulation between the wafer and the contact pads when the contact pads are soldered to an underlying circuit. In some embodiments, before the contact pads are soldered, additional dielectric is grown on the wafer back side without covering the contact pads. In some embodiments, the wafer etch and the fabrication of the additional dielectric are performed one after another by a plasma process while the wafer is held in a non-contact wafer holder. In some embodiments, the wafer is diced and the dice are tested before the etch. The etch and the deposition of the additional dielectric are performed on good dice only. In some embodiments, the dice are not used for vertical integration.

Claims

1. An integrated circuit comprising a die or a wafer comprising:

a semiconductor substrate having one or more through holes passing between a first side and a second side of the substrate, wherein at least one of the through holes widens as it goes through semiconductor material of the substrate from the second side of the substrate to the first side of the substrate;

a transistor having at least a portion of which is formed over the first side of the substrate;

a dielectric in each of the through holes, wherein the dielectric in each through hole protrudes out of the through hole out of the semiconductor material of the substrate on the second side; and

one or more conductive contacts formed in the one or more through holes, wherein the conductive contact formed in each through hole protrudes out of the through hole out of the semiconductor material of the substrate on the second side.

2. The integrated circuit of claim 1 wherein the dielectric around each contact protrudes out of the semiconductor material on the second side by at least 8 μ

m measured in the direction perpendicular to the second side.

3. The integrated circuit of claim 1 further comprising dielectric that covers the second side but does not cover the one or more contacts.

4. The integrated circuit of claim 1 in combination with one or more other integrated circuits such that at least one of the contacts contacts a conductive contact on another integrated circuit, the combination forming a vertical integrated circuit.

5. The integrated circuit of claim 1 further comprising a first circuit element at least a portion of which is formed in the semiconductor substrate.

6. The integrated circuit of claim 5 wherein the first circuit element is a transistor, a capacitor, or a resistor.

7. The integrated circuit of claim 1 wherein the integrated circuit is manufactured using a process comprising:

forming one or more openings in the first side of the substrate;

forming the dielectric and the conductor in each of the one or more openings;

removing material from the second side of the substrate to expose the dielectric on the second side without exposing the conductor;

simultaneously etching the material of the substrate and the dielectric on the second side of the substrate by a process which etches the material of the substrate faster than the dielectric and which etches the dielectric isotropically.

8. The integrated circuit of claim 7 wherein forming one or more openings comprises forming one or more openings each of which widens as it goes from the second side of the substrate to the first side of the substrate.

9. The integrated circuit of claim 7 wherein the integrated circuit is manufactured using a process comprising:

forming one or more openings in the first side of the substrate such that each of the one or more openings widens as it goes from the second side of the substrate to the first side of the substrate;

forming the dielectric on the sidewalls of each opening, and forming the conductor in each opening;

removing material from the second side of the substrate to expose the dielectric on the second side without exposing the conductor;

simultaneously etching the material of the substrate and the dielectric on the second side of the substrate by a process which etches the material of the substrate faster than the dielectric.

10. An integrated circuit comprising a die or a wafer comprising:

a semiconductor substrate having a through hole passing between a first side and a second side of the substrate, wherein the through hole widens as it goes through semiconductor material of the substrate from the second side of the substrate to the first side of the substrate;

a dielectric formed in the through hole and protruding out of the through hole out of the semiconductor material of the substrate on the second side; and

a conductive layer of a uniform composition formed in the through hole and separated in the through hole from the semiconductor material of the substrate by the dielectric, wherein the conductive layer protrudes out of the through hole out of the semiconductor material of the substrate on the second side farther than the dielectric but does not extend away from the through hole over the substrate on the second side.

11. The integrated circuit of claim 10 wherein the conductive layer extends away from the through hole over the substrate on the first side.

12. The integrated circuit of claim 10 wherein a protrusion of the conductive layer on the second side forms a contact pad available for being attached to a circuit external to the die or wafer.

13. The integrated circuit of claim 10 wherein the conductive layer protrudes on the second side farther than any dielectric in the die or wafer.

14. The integrated circuit of claim 10 comprising a transistor having at least a portion formed over the first side of the substrate.