Substrate layout method and structure for reducing cross talk of adjacent signals

• US 20020074162A1
• Filed: 06/20/2001
• Published: 06/20/2002
• Est. Priority Date: 12/15/2000
• Status: Abandoned Application

• Current Assignee: Bor-Ray Su, Chin-Chih Li
• Original Assignee: Bor-Ray Su, Chin-Chih Li
• Inventors: Li, Chin-Chih, Su, Bor-Ray
• Application Number:
  US09/884,132
• Publication Number:
  US 20020074162A1
• Time in Patent Office: Days
• US Class Current: 174/262
• CPC Class Codes: H01L 2223/6611 Wire connections
• CPC Class Codes: H01L 2224/05553 being rectangular
• CPC Class Codes: H01L 2224/05599 Material
• CPC Class Codes: H01L 2224/45099 Material
• CPC Class Codes: H01L 2224/48091 Arched
• CPC Class Codes: H01L 2224/48227 connecting the wire to a bond pad of the item
• CPC Class Codes: H01L 2224/48233 connecting the wire to a potential ring of the item
• CPC Class Codes: H01L 2224/4911 the connectors being bonded to at least one common bonding area, e.g. daisy chain
• CPC Class Codes: H01L 2224/49431 on the semiconductor or solid-state body
• CPC Class Codes: H01L 2224/85399 Material
• CPC Class Codes: H01L 23/49838 Geometry or layout
• CPC Class Codes: H01L 23/552 Protection against radiation, e.g. light or electromagnetic waves
• CPC Class Codes: H01L 24/06 of a plurality of bonding areas
• CPC Class Codes: H01L 24/48 of an individual wire connector
• CPC Class Codes: H01L 24/49 of a plurality of wire connectors
• CPC Class Codes: H01L 2924/00012 Relevant to the scope of the group, the symbol of which is combined with the symbol of this group
• CPC Class Codes: H01L 2924/00014 the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/014 Solder alloys
• CPC Class Codes: H01L 2924/14 Integrated circuits
• CPC Class Codes: H01L 2924/15173 in a single layer of the multilayer substrate
• CPC Class Codes: H01L 2924/15311 : being a ball array, e.g. BGA
• CPC Class Codes: H01L 2924/181 : Encapsulation
• CPC Class Codes: H01L 2924/19107 : off-chip wires

Abstract

The invention provides a substrate layout method and structure of a ball grid array to reduce cross talk of adjacent signals. The substrate comprises a plurality of signal pads formed on a die, a ring around the die, and a plurality of signal fingers around the ring. The substrate layout method for reducing cross talk of adjacent signals is as follows: First, forming a guard pad between two adjacent signal pads. Second, forming a guard finger between two adjacent signal fingers. Next, forming a bonding wire to connect the guard pad to the ring. Then, forming another bonding wire to connect the ring to the guard finger. Subsequently, forming a guard trace to connect the guard finger to a via at the edge of the substrate, and connecting the guard trace to a short-circuiting place through the via.

Claims

1. A substrate layout method for reducing cross talk of adjacent signals, the substrate having a plurality of signal pads formed on a die, a ring around said die, and a plurality of signal fingers around said ring, the substrate layout method comprising:

forming a guard pad between two adjacent signal pads;

forming a guard finger between two adjacent signal fingers;

forming a first bonding wire to connect said guard pad to said ring;

forming a second bonding wire to connect said ring to said guard finger; and

forming a guard trace to connect said guard finger to a via at the edge of the substrate, and connecting said guard trace to a short-circuiting place through said via.

2. The substrate layout method as claimed in claim 1, wherein the substrate is a ball grid array.

3. The substrate layout method as claimed in claim 1, wherein said guard pad is selected from the group consisting of a power and ground pad.

4. The substrate layout method as claimed in claim 1, wherein said ring is selected from the group consisting of a power and ground ring.

5. The substrate layout method as claimed in claim 1, wherein said short-circuiting place is selected from the group consisting of a power and ground plane of the substrate.

6. The substrate layout method as claimed in claim 1, wherein said short-circuiting place is selected from the group consisting of a power and ground solder ball under the substrate.

7. A substrate layout structure for reducing cross talk of adjacent signals, the substrate having a plurality of signal pads formed on a die, a ring around said die, and a plurality of signal fingers around said ring, the substrate layout structure comprising:

a guard pad formed between two adjacent signal pads;

a guard finger formed between two adjacent signal fingers;

a first bonding wire for connecting said guard pad to said ring;

a second bonding wire for connecting said ring to said guard finger; and

a guard trace for connecting said guard finger to a via at the edge of the substrate, and connecting said guard trace to a short-circuiting place through said via.

8. The substrate layout method as claimed in claim 7, wherein the substrate is a ball grid array.

9. The substrate layout method as claimed in claim 7, wherein said guard pad is selected from the group consisting of a power and ground pad.

10. The substrate layout method as claimed in claim 7, wherein said ring is selected from the group consisting of a power and ground ring.

11. The substrate layout method as claimed in claim 7, wherein said short-circuiting place is selected from the group consisting of a power and ground plane of the substrate.

12. The substrate layout method as claimed in claim 7, wherein said short-circuiting place is selected from the group consisting of a power and ground solder ball under the substrate.

14. The substrate layout method as claimed in claim 13, wherein said ring is selected from the group consisting of a power and ground ring.

15. The substrate layout method as claimed in claim 13, wherein said short-circuiting place is a power and ground plane of the substrate.

16. The substrate layout method as claimed in claim 13, wherein said short-circuiting place is a power and ground solder ball under the substrate.

18. The substrate layout method as claimed in claim 17, wherein said ring is selected from the group consisting of a power and ground ring.

19. The substrate layout method as claimed in claim 17, wherein said short-circuiting place is selected from the group consisting of a power and ground plane of the substrate.

20. The substrate layout method as claimed in claim 17, wherein said short-circuiting place is selected from the group consisting of a power and ground solder ball under the substrate.

13. A substrate layout method for reducing cross talk of adjacent signals, the substrate having a plurality of signal pads formed on a die, a ring around said die, and a plurality of signal fingers around said ring, the substrate layout method comprising:

forming a guard finger between two adjacent signal fingers;

forming a bonding wire to connect said ring to said guard finger; and

forming a guard trace to connect said guard finger to a via at the edge of the substrate, and connecting said guard trace to a short-circuiting place through said via.

17. A substrate layout structure for reducing cross talk of adjacent signals, the substrate having a plurality of signal pads formed on a die, a ring around said die, and a plurality of signal fingers around said ring, the substrate layout structure comprising:

a guard finger formed between two adjacent signal fingers;

a bonding wire for connecting said ring to said guard finger; and

a guard trace for connecting said guard finger to a via at the edge of the substrate, and connecting said guard trace to a short-circuiting place through said via.