P-i-n transit time silicon-on-insulator device

• US 20020100950A1
• Filed: 01/23/2002
• Published: 08/01/2002
• Est. Priority Date: 01/31/2001
• Status: Active Grant

• Current Assignee: M2 Networks, Inc., Texas Instruments, Inc.
• Original Assignee: M2 Networks, Inc.
• Inventors: Pinto, Angelo, Howard, Gregory E., Babcock, Jeffrey A., Steinmann, Phillipp
• Granted Patent: US 6,660,616 B2
• Time in Patent Office: Days
• US Class Current: 257/461
• CPC Class Codes: H01L 29/868 PIN diodes

Abstract

A transit time device (15, 15′) in a silicon-on-insulator (SOI) technology is disclosed. An anode region (18) and a cathode region (20) are formed on opposing ends of an epitaxial layer (14), with an intrinsic or lightly-doped region (22) disposed therebetween. Sinker structures (30p, 30n) are formed in an overlying epitaxial layer (24) over and in contact with the anode and cathode regions (18, 20). A charge injection terminal may be formed in a sinker structure (32n) in the overlying epitaxial layer (24), if the transit time device (15′) is of the three-terminal type. The device (15, 15′) has extremely low parasitic capacitance to substrate, because of the buried oxide layer (12) underlying the intrinsic region (22).

Claims

1. A method of forming a transit time device in a semiconductor layer overlying an insulator layer, comprising the steps of:

masking the semiconductor layer to expose a first selected location of the semiconductor layer;

doping the exposed first selected location to a first conductivity type;

masking the semiconductor layer to expose a second selected location of the semiconductor layer, the first and second selected locations separated from one another by a distance;

doping the exposed second selected location to a second conductivity type, so that a portion of the semiconductor layer remaining between the first and second doped selected locations corresponds to an intrinsic region; and

forming an isolation structure to surround the first and second doped selected locations and the intrinsic region.

2. The method of claim 1, further comprising:

doping the intrinsic region to a lightly-doped doping concentration relative to the first and second doped selected locations.

3. The method of claim 1, further comprising:

after the doping steps, forming an epitaxial layer over the semiconductor layer;

removing selected portions of the epitaxial layer, leaving first and second sinker structures overlying and in contact with the first and second doped selected locations of the semiconductor;

doping the first and second sinker structures to the first and second conductivity types, respectively.

4. The method of claim 3, wherein the step of forming an isolation structure comprises:

after the removing step, removing portions of the semiconductor layer surrounding the first and second doped selected locations and the intrinsic region;

then depositing an insulator at the locations of the removed portions of the semiconductor layer, and also the at the locations of the removed portions of the epitaxial layer.

5. The method of claim 3, wherein the removing step also leaves a charge injection sinker structure overlying and in contact with the intrinsic region;

and wherein the doping step also dopes the charge injection sinker structure to one of the first and second conductivity types.

6. The method of claim 5, wherein the step of forming an isolation structure comprises:

after the removing step, removing portions of the semiconductor layer surrounding the first and second doped selected locations and the intrinsic region;

then depositing an insulator at the locations of the removed portions of the semiconductor layer, and also the at the locations of the removed portions of the epitaxial layer.

7. The method of claim 5, further comprising:

cladding a surface of each of the sinker structures and charge injection sinker structure, with a refractory metal silicide.

8. The method of claim 4, further comprising:

cladding a surface of each of the sinker structures and charge injection sinker structure, with a refractory metal silicide.

9. A integrated circuit structure including a transit time device, comprising:

a handle wafer;

an insulator layer overlying a surface of the handle wafer;

a single-crystal silicon layer overlying the insulator layer, having first and second doped regions disposed near opposing ends, the first and second doped regions being doped to first and second conductivity types, respectively, and the first and second doped regions being heavily doped relative to a portion of the silicon layer disposed therebetween; and

a deep insulator structure surrounding the silicon layer.

10. The structure of claim 9, further comprising:

a first sinker structure, extending from the first doped region, and comprising silicon doped to the first conductivity type;

a second sinker structure, extending from the second doped region, and comprising silicon doped to the second conductivity type.

11. The structure of claim 10, further comprising:

a shallow insulator structure disposed over the silicon layer and the deep insulator structure, through which the first and second sinker structures extend.

12. The structure of claim 10, further comprising:

a charge injection sinker structure, extending from the portion of the silicon layer disposed between the first and second doped regions, and doped to one of the first and second conductivity types.

13. The structure of claim 12, further comprising:

a shallow insulator structure disposed over the silicon layer and the deep insulator structure, through which the first, second, and charge injection sinker structures extend.

14. The structure of claim 13, further comprising:

refractory metal silicide cladding disposed at the surface of each of the first, second, and charge injection sinker structures.

15. The structure of claim 9, wherein the portion of the silicon layer disposed between the first and second doped regions is substantially intrinsic silicon.

16. The structure of claim 9, wherein the portion of the silicon layer disposed between the first and second doped regions is lightly-doped silicon.

17. The structure of claim 10, wherein the first and second sinker structures are at least partially etched;

and further comprising;

conductive material disposed into the etched portions of the first and second sinker structures, for making electrical connection to the first and second doped regions.

18. The structure of claim 10, wherein the first and second sinker structures are at least partially etched;

and further comprising;

a charge injection sinker structure, extending from the portion of the silicon layer disposed between the first and second doped regions, and doped to one of the first and second conductivity types; and

conductive material disposed into the etched portions of the first, second, and charge injection sinker structures, for making electrical connection to the first and second doped regions.