Method of de-allocating multiple processor cores for an L2 correctable error

• US 20020133759A1
• Filed: 03/01/2001
• Published: 09/19/2002
• Est. Priority Date: 03/01/2001
• Status: Active Grant

• Current Assignee: International Business Machines Corporation
• Original Assignee: International Business Machines Corporation
• Inventors: Bailey, Sheldon Ray, Kobler, Michael Alan, Lim, Michael Youhour, Werbner, Stuart Allen
• Granted Patent: US 6,742,145 B2
• Time in Patent Office: Days
• US Class Current: 714/54
• CPC Class Codes: G06F 11/0724 in a multiprocessor or a multi-core unit multiprocessors per se G06F15/80
• CPC Class Codes: G06F 11/0775 Content or structure details of the error report, e.g. specific table structure, specific error fields
• CPC Class Codes: G06F 11/0793 Remedial or corrective actions recovery from an exception in an instruction pipeline G06F9/3861; by retry G06F11/1402; for recovering from a failure of a protocol instance or entity H04L69/40

Abstract

A method of de-allocating multiple processor cores sharing a failing bank of memory is disclosed. The method allows new multiple-processor integrated circuits with on-chip shared memory to be de-allocated using existing technology designed for use with single-processor integrated circuit technology.

Claims

1. A method for handling a hardware error in a multiple-processor computer system, comprising the steps of:

(a) identifying a plurality of processors associated with a shared hardware component;

(b) detecting a failure of the shared hardware component; and

(c) responsive to step (b), reporting a plurality of errors, wherein each of the plurality of errors is associated with one of the plurality of processors.

2. The method of claim 1, wherein the plurality of errors is reported by entering the plurality of errors into an error log as a plurality of entries.

3. The method of claim 2, wherein each of the plurality of entries is associated with only one processor from the plurality of processors.

4. The method of claim 1, wherein the plurality of errors is reported by entering the plurality of errors into a plurality of error logs.

5. The method of claim 4, wherein each of the plurality of error logs is associated with only one processor from the plurality of processors.

6. The method of claim 1, wherein the shared hardware component is memory.

7. The method of claim 6, wherein the memory forms a secondary cache.

8. The method of claim 1, comprising the step of:

(d) responsive to step (c), disabling the plurality of processors.

9. The method of claim 1, wherein the plurality of processors and the shared hardware component are formed using a single integrated circuit.

10. The method of claim 9, wherein the plurality of errors is reported by entering the plurality of errors into an error log as a plurality of entries.

11. The method of claim 10, wherein each of the plurality of entries is associated with only one processor from the plurality of processors.

12. The method of claim 9, wherein the shared hardware component is memory.

13. The method of claim 12, wherein the memory forms a secondary cache.

14. The method of claim 9, comprising the step of:

(d) responsive to step (c), disabling the plurality of processors.

16. The computer program product of claim 15, wherein the plurality of errors is reported by entering the plurality of errors into an error log as a plurality of entries.

17. The computer program product of claim 16, wherein each of the plurality of entries is associated with only one processor from the plurality of processors.

18. The computer program product of claim 15, wherein the plurality of errors is reported by entering the plurality of errors into a plurality of error logs.

19. The computer program product of claim 18, wherein each of the plurality of error logs is associated with only one processor from the plurality of processors.

20. The computer program product of claim 15, wherein the shared hardware component is memory.

21. The computer program product of claim 20, wherein the memory forms a secondary cache.

22. The computer program product of claim 15, comprising instructions for:

(d) responsive to the instructions for (c), disabling the plurality of processors.

23. The computer program product of claim 15, wherein the plurality of processors and the shared hardware component are formed using a single integrated circuit.

24. The computer program product of claim 23, wherein the plurality of errors is reported by entering the plurality of errors into an error log as a plurality of entries.

25. The computer program product of claim 24, wherein each of the plurality of entries is associated with only one processor from the plurality of processors.

26. The computer program product of claim 23, wherein the shared hardware component is memory.

27. The computer program product of claim 26, wherein the memory forms a secondary cache.

28. The computer program product of claim 23, comprising instructions for:

(d) responsive to the instructions for (c), disabling the plurality of processors.

30. The system of claim 29, comprising an error log, wherein the plurality of errors is reported by entering the plurality of errors into an error log as a plurality of entries.

31. The system of claim 30, wherein each of the plurality of entries is associated with only one processor from the plurality of processors.

32. The system of claim 29, wherein the plurality of errors is reported by entering the plurality of errors into a plurality of error logs.

33. The system of claim 32, wherein each of the plurality of error logs is associated with only one processor from the plurality of processors.

34. The system of claim 29, wherein the hardware component is memory.

35. The system of claim 34, wherein the memory forms a secondary cache.

36. The system of claim 29, wherein responsive to the plurality of errors being reported, the operating system disables the plurality of processors.

37. The system of claim 29, wherein the plurality of processors and the hardware component are formed using a single integrated circuit.

38. The system of claim 37, comprising an error log, wherein the plurality of errors is reported by entering the plurality of errors into an error log as a plurality of entries.

39. The system of claim 38, wherein each of the plurality of entries is associated with only one processor from the plurality of processors.

40. The system of claim 37, wherein the hardware component is memory.

41. The system of claim 40, wherein the memory forms a secondary cache.

42. The system of claim 37, wherein responsive to the plurality of errors being reported, the operating system disables the plurality of processors.

15. A computer program product, in a computer-readable medium, for handling a hardware error in a multiple-processor computer system, comprising instructions for:

(a) identifying a plurality of processors associated with a shared hardware component;

(b) detecting a failure of the shared hardware component; and

(c) responsive to the instructions for (b), reporting a plurality of errors, wherein each of the plurality of errors is associated with one of the plurality of processors.

29. A system for fault-tolerant computing in a multiple-processor data processing environment, comprising:

a plurality of processors;

a hardware component shared by the plurality of processors;

a common service processor; and

an operating system,

wherein if the hardware component fails, the common service processor reports to the operating system a plurality of errors wherein each of the plurality of errors is associated with one of the plurality of processors.