Method of de-allocating multiple processor cores for an L2 correctable error
First Claim
Patent Images
1. A method for handling a hardware error in a multiple-processor computer system, comprising the steps of:
- (a) identifying a plurality of processors associated with a shared hardware component;
(b) detecting a failure of the shared hardware component; and
(c) responsive to step (b), reporting a plurality of errors, wherein each of the plurality of errors is associated with one of the plurality of processors.
1 Assignment
0 Petitions
Accused Products
Abstract
A method of de-allocating multiple processor cores sharing a failing bank of memory is disclosed. The method allows new multiple-processor integrated circuits with on-chip shared memory to be de-allocated using existing technology designed for use with single-processor integrated circuit technology.
31 Citations
42 Claims
-
1. A method for handling a hardware error in a multiple-processor computer system, comprising the steps of:
-
(a) identifying a plurality of processors associated with a shared hardware component;
(b) detecting a failure of the shared hardware component; and
(c) responsive to step (b), reporting a plurality of errors, wherein each of the plurality of errors is associated with one of the plurality of processors. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14)
(d) responsive to step (c), disabling the plurality of processors.
-
-
9. The method of claim 1, wherein the plurality of processors and the shared hardware component are formed using a single integrated circuit.
-
10. The method of claim 9, wherein the plurality of errors is reported by entering the plurality of errors into an error log as a plurality of entries.
-
11. The method of claim 10, wherein each of the plurality of entries is associated with only one processor from the plurality of processors.
-
12. The method of claim 9, wherein the shared hardware component is memory.
-
13. The method of claim 12, wherein the memory forms a secondary cache.
-
14. The method of claim 9, comprising the step of:
(d) responsive to step (c), disabling the plurality of processors.
-
15. A computer program product, in a computer-readable medium, for handling a hardware error in a multiple-processor computer system, comprising instructions for:
-
(a) identifying a plurality of processors associated with a shared hardware component;
(b) detecting a failure of the shared hardware component; and
(c) responsive to the instructions for (b), reporting a plurality of errors, wherein each of the plurality of errors is associated with one of the plurality of processors. - View Dependent Claims (16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28)
(d) responsive to the instructions for (c), disabling the plurality of processors.
-
-
23. The computer program product of claim 15, wherein the plurality of processors and the shared hardware component are formed using a single integrated circuit.
-
24. The computer program product of claim 23, wherein the plurality of errors is reported by entering the plurality of errors into an error log as a plurality of entries.
-
25. The computer program product of claim 24, wherein each of the plurality of entries is associated with only one processor from the plurality of processors.
-
26. The computer program product of claim 23, wherein the shared hardware component is memory.
-
27. The computer program product of claim 26, wherein the memory forms a secondary cache.
-
28. The computer program product of claim 23, comprising instructions for:
(d) responsive to the instructions for (c), disabling the plurality of processors.
-
29. A system for fault-tolerant computing in a multiple-processor data processing environment, comprising:
-
a plurality of processors;
a hardware component shared by the plurality of processors;
a common service processor; and
an operating system, wherein if the hardware component fails, the common service processor reports to the operating system a plurality of errors wherein each of the plurality of errors is associated with one of the plurality of processors. - View Dependent Claims (30, 31, 32, 33, 34, 35, 36, 37, 38, 39, 40, 41, 42)
-
Specification