Word line driver for a semiconductor memory device
First Claim
1. A method for discharging a word line comprising:
- coupling the word line to a first power supply; and
diverting current from the word line to a second power supply.
1 Assignment
0 Petitions
Accused Products
Abstract
A memory device utilizing a negatively biased word line scheme diverts word line discharge current from the negative voltage source during a precharge operation, thereby reducing voltage fluctuations and current consumption from the negative voltage source. A main word line, sub-word line, word line enable signal, or other type of word line is coupled to the negative voltage source during a precharge operation. The word line is also coupled to a second power supply during the precharge operation, and then uncoupled from the second power supply after most of the word line discharge current has been diverted. The negative voltage source can then discharge and maintain the word line at a negative bias.
10 Citations
68 Claims
-
1. A method for discharging a word line comprising:
-
coupling the word line to a first power supply; and
diverting current from the word line to a second power supply. - View Dependent Claims (4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 19, 20)
-
-
3. A method according to claim 1 wherein coupling the word line to the first power supply comprises coupling the word line to the first power supply responsive to row address information.
-
18. A method for discharging a word line comprising:
-
coupling the word line to a first power supply; and
diverting current from the word line to a second power supply responsive to a voltage of the word line.
-
-
21. A method for discharging a word line comprising:
-
coupling the word line to a first power supply; and
diverting current from the word line to a second power supply responsive to a row address. - View Dependent Claims (2, 22, 24, 25, 27, 28, 29)
-
-
23. A method according to claim 21 wherein:
-
the first power supply is a negative power supply; and
the second power supply is a ground power supply.
-
-
23-1. A method for discharging a word line comprising:
-
coupling the word line to a first power supply; and
diverting current from the word line to a second power supply;
wherein diverting current from the word line to the second power supply comprises;
coupling the word line to the second power supply, and uncoupling the word line from the second power supply after substantial word line discharge current has been diverted to the second power supply.
-
-
26. A method for discharging a sub-word line coupled to a sub-word line driver which is driven by a word line enable signal decoded by an upper row address and a PX line decoded by a lower row address, the method comprising:
-
coupling the sub-word line to a first power supply;
diverting current from the sub-word line to a second power supply; and
coupling the word line enable signal to the first power supply.
-
-
27-2. A method according to claim 26 further comprising diverting current from the word line enable signal to the second power supply.
-
30. A semiconductor memory device comprising:
-
a word line; and
a word line driver circuit coupled to the word line and adapted to couple the word line to a first power supply during a precharge operation;
wherein the word line driver circuit is adapted to divert word line discharge current to a second power supply during the precharge operation. - View Dependent Claims (31, 32, 33, 34, 35, 36, 37, 38, 39, 40, 41, 42, 43, 44, 45, 47, 49, 50)
-
-
46. A semiconductor memory device comprising:
-
a plurality of word lines; and
a plurality of word line driver circuits coupled to the word lines and adapted to couple the word lines to a first power supply during a precharge operation;
wherein the word line driver circuits are adapted to divert word line discharge current to a second power supply responsive to a voltage of the corresponding word line during the precharge operation for each word line.
-
-
48. A semiconductor memory device according to claim 46 wherein:
-
the first power supply is a negative power supply; and
the second power supply is a ground power supply.
-
-
48-3. A semiconductor memory device comprising:
-
a plurality of word lines; and
a plurality of word line driver circuits coupled to the word lines and adapted to couple the word lines to a first power supply during a precharge operation;
wherein the word line driver circuits are adapted to divert word line discharge current to a second power supply responsive to a row address during the precharge operation for each word line.
-
-
51. A semiconductor memory device comprising:
-
a plurality of sub-word lines;
a plurality of sub-word line drivers coupled to the sub-word lines and adapted to couple the sub-word lines to a first power supply responsive to a plurality of word line enable signals and a plurality of PX signals during a precharge operation;
a plurality of PX signal generators coupled to the plurality of sub-word line drivers and adapted to generate the plurality of PX signals responsive to a lower row address; and
a row decoder coupled to the plurality of sub-word line drivers and adapted to generate the plurality of word line enable signals responsive to an upper row address;
wherein the plurality of PX signal generators are adapted to divert sub-word line discharge current to a second power supply responsive to the lower row address during the precharge operation for each word line. - View Dependent Claims (52, 53, 54)
-
-
55. A semiconductor memory device comprising:
-
a plurality of sub-word lines;
a plurality of sub-word line drivers coupled to the sub-word lines and adapted to couple the sub-word lines to a first power supply responsive to a plurality of word line enable signals and a plurality of PX signals during a precharge operation;
a plurality of PX signal generators coupled to the plurality of sub-word line drivers and adapted to generate the plurality of PX signals responsive to a lower row address;
a row decoder coupled to the plurality of sub-word line drivers and adapted to generate the plurality of word line enable signals responsive to an upper row address; and
a plurality of power supply keeping circuits coupled to the word line enable signals and adapted to coupled the word line enable signals to the first power supply responsive to a voltage of each word line enable signal;
wherein the row decoder is adapted to divert word line enable signal discharge current to a second power supply responsive to the upper row address during the precharge operation for each word line. - View Dependent Claims (56, 58, 59, 60)
-
-
57. A semiconductor memory device comprising:
-
a word line;
means for coupling the word line to a first power supply during a precharge operation; and
means for diverting current from the word line to a second power supply during the precharge operation.
-
-
61. A semiconductor memory device comprising:
-
a sub-word line;
means for driving the sub-word line responsive to a PX signal and a word line enable signal;
means for generating the PX signal responsive to a lower row address;
means for generating the word line enable signal responsive to an upper row address; and
means for coupling the word line enable signal to a first power supply during a precharge operation;
wherein the means for generating the PX signal is adapted to divert current from the sub-word line to a second power supply during the precharge operation. - View Dependent Claims (62, 63, 64)
-
-
66. A semiconductor memory device comprising:
-
a sub-word line;
means for driving the sub-word line responsive to a PX signal and a word line enable signal;
means for generating the PX signal responsive to a lower row address; and
means for generating the word line enable signal responsive to an upper row address;
wherein the means for driving the sub-word line is adapted to couple the sub-word line to a first power supply during a precharge operation; and
wherein the means for generating the PX signal is adapted to divert current from the sub-word line to a second power supply during the precharge operation. - View Dependent Claims (67, 68)
-
Specification