Negatively biased word line scheme for a semiconductor memory device

• US 6,545,923 B2
• Filed: 07/09/2001
• Issued: 04/08/2003
• Est. Priority Date: 05/04/2001
• Status: Expired due to Fees

• Current Assignee: Samsung Electronics Co. Ltd.
• Original Assignee: Samsung Electronics Co. Ltd.
• Inventors: Sim, Jae-Yoon, Yoo, Jei-Hwan
• Primary Examiner(s): Tran, Andrew Q.
• Application Number:
  US09/901,785
• Publication Number:
  US 20020163843A1
• Time in Patent Office: 638 Days
• Field of Search: 365/204, 365/230.06, 365/227, 365/228, 365/226, 365/195, 365/191
• US Class Current: 365/204
• CPC Class Codes: G11C 11/4085 Word line control circuits, e.g. word line drivers, - boosters, - pull-up, - pull-down, - precharge
• CPC Class Codes: G11C 8/08 Word line control circuits, e.g. drivers, boosters, pull-up circuits, pull-down circuits, precharging circuits, for word lines

Abstract

A memory device utilizing a negatively biased word line scheme diverts word line discharge current from the negative voltage source during a precharge operation, thereby reducing voltage fluctuations and current consumption from the negative voltage source. A main word line, sub-word line, word line enable signal, or other type of word line is coupled to the negative voltage source during a precharge operation. The word line is also coupled to a second power supply during the precharge operation, and then uncoupled from the second power supply after most of the word line discharge current has been diverted. The negative voltage source can then discharge and maintain the word line at a negative bias.

Claims

1. A method for discharging a word line comprising:

coupling the word line to a first power supply; and

diverting current from the word line to a second power supply.

2. A method according to claim 1 wherein coupling the word line to the first power supply comprises coupling the word line to the first power supply responsive to a voltage of the word line.

3. A method according to claim 1 wherein coupling the word line to the first power supply comprises coupling the word line to the first power supply responsive to row address information.

4. A method according to claim 1 wherein the word line is a main word line.

5. A method according to claim 4 wherein diverting current from the word line to the second power supply comprises:

coupling the word line to the second power supply; and

uncoupling the word line from the second power supply after substantial word line discharge current has been diverted to the second power supply.

6. A method according to claim 5 wherein coupling the word line to the second power supply comprises coupling the word line to the second power supply responsive to row address information.

7. A method according to claim 5 wherein uncoupling the word line from the second power supply comprises turning off a diode when a voltage of the word line reaches a threshold voltage of the diode.

8. A method according to claim 1 wherein the word line is a sub-word line which is driven by a sub-word line driver responsive to a word line enable signal and a PX line.

9. A method according to claim 8 further comprising coupling the word line enable signal to the first power supply.

10. A method according to claim 9 wherein coupling the word line enable signal to the first power supply comprises coupling the word line enable signal to the first power supply responsive to a voltage of the word line enable signal.

11. A method according to claim 9 wherein coupling the word line enable signal to the first power supply comprises coupling the word line enable signal to the first power supply responsive to row address information.

12. A method according to claim 11 wherein the word line enable signal is coupled to the first power supply through a transistor having the same cell Vth implantation process that is used to fabricate cell access transistors.

13. A method according to claim 9 further comprising diverting current from the word line enable signal to the second power supply.

14. A method according to claim 13 wherein current is diverted from the word line enable signal to the second power supply responsive to row address information.

15. A method according to claim 8 wherein diverting current from the word line to the second power supply comprises:

driving the PX line with an inverter referenced to the second power supply; and

uncoupling the inverter from the second power supply after substantial word line discharge current has been diverted to the second power supply.

16. A method according to claim 15 wherein uncoupling the inverter from the second power supply comprises uncoupling the inverter responsive to a voltage of the PX line.

17. A method according to claim 8 further comprising coupling the PX line to the first power supply responsive to row address information.

18. A method for discharging a word line comprising:

coupling the word line to a first power supply; and

diverting current from the word line to a second power supply responsive to a voltage of the word line.

19. A method according to claim 18 wherein:

the first power supply is a substrate power supply; and

the second power supply is a ground power supply.

20. A method according to claim 18 wherein:

the first power supply is a negative power supply; and

the second power supply is a ground power supply.

21. A method for discharging a word line comprising:

coupling the word line to a first power supply; and

diverting current from the word line to a second power supply responsive to a row address.

22. A method according to claim 21 wherein:

the first power supply is a substrate power supply; and

the second power supply is a ground power supply.

23. A method according to claim 21 wherein:

the first power supply is a negative power supply; and

the second power supply is a ground power supply.

24. A method for discharging a word line comprising:

coupling the word line to a first power supply; and

diverting current from the word line to a second power supply;

wherein diverting current from the word line to the second power supply comprises;

coupling the word line to the second power supply, and

uncoupling the word line from the second power supply after substantial word line discharge current has been diverted to the second power supply.

25. A method according to claim 24 wherein coupling the word line to the second power supply comprises coupling the word line to the second power supply responsive to a voltage of the word line.

26. A method according to claim 24 wherein coupling the word line to the second power supply comprises coupling the word line to the second power supply responsive to a row address.

27. A method for discharging a sub-word line coupled to a sub-word line driver which is driven by a word line enable signal decoded by an upper row address and a PX line decoded by a lower row address, the method comprising:

coupling the sub-word line to a first power supply;

diverting current from the sub-word line to a second power supply; and

coupling the word line enable signal to the first power supply.

28. A method according to claim 27 wherein diverting current from the sub-word line to the second power supply comprises:

coupling the PX line to the second power supply responsive to the lower row address; and

uncoupling the PX line from the second power supply after substantial discharge current has been diverted to the second power supply.

29. A method according to claim 27 further comprising diverting current from the word line enable signal to the second power supply.

30. A method according to claim 29 wherein diverting current from the word line enable signal comprises diverting current from the word line enable signal responsive to a voltage of the word line enable signal.

31. A method according to claim 29 wherein diverting current from the word line enable signal comprises diverting current from the word line enable signal responsive to the upper row address.

32. A semiconductor memory device comprising:

a word line; and

a word line driver circuit coupled to the word line and adapted to couple the word line to a first power supply during a precharge operation;

wherein the word line driver circuit is adapted to divert word line discharge current to a second power supply during the precharge operation.

33. A semiconductor memory device according to claim 32 wherein:

the word line is a main word line; and

the word line driver circuit comprises a drive stage coupled to the main word line and adapted to divert word line discharge current to the second power supply during the precharge operation.

34. A semiconductor memory device according to claim 33 wherein the word line driver circuit further comprises a power supply keeping circuit coupled to the main word line.

35. A semiconductor memory device according to claim 34 wherein the power supply keeping circuit is arranged on a side of a memory array opposite a row decoder.

36. A semiconductor memory device according to claim 34 wherein:

the power supply keeping circuit comprises;

a first transistor coupled between the main word line and the first power supply, and

an inverter coupled between the first transistor and the main word line; and

the drive stage comprises;

a second transistor coupled to the second power supply, and

a diode coupled between the second transistor and the main word line.

37. A semiconductor memory device according to claim 33 wherein the drive stage comprises:

a first transistor arranged to couple the main word line to the first power supply; and

a second transistor arranged to divert word line discharge current to the second power supply.

38. A semiconductor memory device according to claim 32 wherein:

the word line is a sub-word line; and

the word line driver circuit comprises a sub-word line driver circuit adapted to drive the sub-word line responsive to a word line enable signal and a PX line.

39. A semiconductor memory device according to claim 38 wherein the sub-word line driver circuit comprises a transistor coupled between the sub-word line and the first power supply.

40. A semiconductor memory device according to claim 39 wherein the transistor is fabricated with the same cell Vth implantation process that is used to fabricate cell access transistors.

41. A semiconductor memory device according to claim 38 wherein the word line driver circuit further comprises conjunction circuitry coupled to the sub-word line driver circuit and adapted to drive a PXID line and a PXIB line responsive to row address information.

42. A semiconductor memory device according to claim 41 wherein the conjunction circuitry comprises:

an inverter coupled to the PXID line and arranged to divert discharge current from the sub-word line to the second power supply; and

a transistor coupled between the inverter and the second power supply and arranged to uncouple the PXID line from the second power supply after a substantial amount of discharge current has been diverted.

43. A semiconductor memory device according to claim 41 wherein the sub-word line driver circuit comprises:

a first transistor coupled between the PXID line and the sub-word line, and arranged to operate responsive to the word line enable signal; and

a second transistor coupled between the sub-word line and the first power supply, and arranged to operate responsive to the PXIB line.

44. A semiconductor memory device according to claim 43 wherein the conjunction circuitry comprises a third transistor coupled between the PXID line and the first power supply, and arranged to operate responsive to the PXIB line.

45. A semiconductor memory device according to claim 38 wherein the sub-word line driver circuit further comprises a drive stage coupled to the word line enable signal.

46. A semiconductor memory device according to claim 45 wherein:

the drive stage comprises a first transistor coupled to the second power supply and arranged to operate responsive to row address information, and a diode coupled between the first transistor and the word line enable signal; and

the sub-word line driver circuit further comprises a power supply keeping circuit coupled to the word line enable signal.

47. A semiconductor memory device according to claim 46 wherein the power supply keeping circuit comprises:

a transistor coupled between the word line enable signal and the first power supply; and

an inverter coupled between the transistor and the word line enable signal.

48. A semiconductor memory device comprising:

a plurality of word lines; and

a plurality of word line driver circuits coupled to the word lines and adapted to couple the word lines to a first power supply during a precharge operation;

wherein the word line driver circuits are adapted to divert word line discharge current to a second power supply responsive to a voltage of the corresponding word line during the precharge operation for each word line.

49. A semiconductor memory device according to claim 48 wherein:

the first power supply is a substrate power supply; and

the second power supply is a ground power supply.

50. A semiconductor memory device according to claim 48 wherein:

the first power supply is a negative power supply; and

the second power supply is a ground power supply.

51. A semiconductor memory device comprising:

a plurality of word lines; and

a plurality of word line driver circuits coupled to the word lines and adapted to couple the word lines to a first power supply during a precharge operation;

wherein the word line driver circuits are adapted to divert word line discharge current to a second power supply responsive to a row address during the precharge operation for each word line.

52. A semiconductor memory device according to claim 51 wherein:

the first power supply is a substrate power supply; and

the second power supply is a ground power supply.

53. A semiconductor memory device according to claim 51 wherein:

the first power supply is a negative power supply; and

the second power supply is a ground power supply.

54. A semiconductor memory device comprising:

a plurality of sub-word lines;

a plurality of sub-word line drivers coupled to the sub-word lines and adapted to couple the sub-word lines to a first power supply responsive to a plurality of word line enable signals and a plurality of PX signals during a precharge operation;

a plurality of PX signal generators coupled to the plurality of sub-word line drivers and adapted to generate the plurality of PX signals responsive to a lower row address; and

a row decoder coupled to the plurality of sub-word line drivers and adapted to generate the plurality of word line enable signals responsive to an upper row address;

wherein the plurality of PX signal generators are adapted to divert sub-word line discharge current to a second power supply responsive to the lower row address during the precharge operation for each word line.

55. A semiconductor memory device according to claim 54 wherein the row decoder is adapted to divert word line enable signal discharge current to the second power supply responsive to the upper row address during the precharge operation for each word line.

56. A semiconductor memory device according to claim 55 further comprising a plurality of power supply keeping circuits coupled to the word line enable signals and adapted to couple the word line enable signals to the first power supply responsive to a voltage of each word line enable signal.

57. A semiconductor memory device according to claim 54 wherein the row decoder is adapted to couple the word line enable signals to the first power supply responsive to the upper row address during the precharge operation for each word line.

58. A semiconductor memory device comprising:

a plurality of sub-word lines;

a plurality of sub-word line drivers coupled to the sub-word lines and adapted to couple the sub-word lines to a first power supply responsive to a plurality of word line enable signals and a plurality of PX signals during a precharge operation;

a plurality of PX signal generators coupled to the plurality of sub-word line drivers and adapted to generate the plurality of PX signals responsive to a lower row address;

a row decoder coupled to the plurality of sub-word line drivers and adapted to generate the plurality of word line enable signals responsive to an upper row address; and

a plurality of power supply keeping circuits coupled to the word line enable signals and adapted to couple the word line enable signals to the first power supply responsive to a voltage of each word line enable signal;

wherein the row decoder is adapted to divert word line enable signal discharge current to a second power supply responsive to the upper row address during the precharge operation for each word line.

59. A semiconductor memory device according to claim 58 wherein the row decoder is adapted to couple each word line enable signal to the second power supply responsive to the upper row address and uncouples each word line enable signal from the second power supply responsive to a voltage of each word line enable signal.

60. A semiconductor memory device comprising:

a word line;

means for coupling the word line to a first power supply during a precharge operation; and

means for diverting current from the word line to a second power supply during the precharge operation.

61. A semiconductor memory device according to claim 60 wherein:

the word line is a main word line; and

the means for diverting current from the word line to the second power supply comprises a drive stage.

62. A semiconductor memory device according to claim 61 wherein the means for coupling the word line to the first power supply comprises a power supply keeping circuit.

63. A semiconductor memory device according to claim 60 wherein:

the word line is a sub-word line; and

the means for diverting current from the word line to the second power supply comprises;

a sub-word line driver circuit coupled to the sub-word line, and

a conjunction circuit coupled to the sub-word line driver circuit and adapted to couple the sub-word line to the second power supply during the precharge operation and uncouple the sub-word line from the second power supply after substantial discharge current has been diverted to the second power supply.

64. A semiconductor memory device comprising:

a sub-word line;

means for driving the sub-word line responsive to a PX signal and a word line enable signal;

means for generating the PX signal responsive to a lower row address;

means for generating the word line enable signal responsive to an upper row address; and

means for coupling the word line enable signal to a first power supply during a precharge operation;

wherein the means for generating the PX signal is adapted to divert current from the sub-word line to a second power supply during the precharge operation.

65. A semiconductor memory device according to claim 64 wherein the means for coupling the word line enable signal to a first power supply comprises a power supply keeping circuit.

66. A semiconductor memory device according to claim 64 wherein the means for generating the word line enable signal is adapted to divert word line enable signal discharge current to the second power supply during the precharge operation.

67. A semiconductor memory device according to claim 64 wherein the means for driving the sub-word line is adapted to couple the sub-word line to the first power supply during the precharge operation.

68. A semiconductor memory device comprising:

a sub-word line;

means for driving the sub-word line responsive to a PX signal and a word line enable signal;

means for generating the PX signal responsive to a lower row address; and

means for generating the word line enable signal responsive to an upper row address;

wherein the means for driving the sub-word line is adapted to couple the sub-word line to a first power supply during a precharge operation; and

wherein the means for generating the PX signal is adapted to divert current from the sub-word line to a second power supply during the precharge operation.

69. A semiconductor memory device according to claim 68 wherein the means for generating the word line enable signal is adapted to couple the word line enable signal to the first power supply during the precharge operation.

70. A semiconductor memory device according to claim 68 wherein the means for generating the word line enable signal is adapted to divert word line enable signal discharge current to the second power supply during the precharge operation.