Non-volatile memory and method of manufacturing the same

• US 20020179964A1
• Filed: 04/24/2002
• Published: 12/05/2002
• Est. Priority Date: 04/24/2001
• Status: Abandoned Application

• Current Assignee: Semiconductor Energy Laboratory Co., Ltd.
• Original Assignee: Semiconductor Energy Laboratory Co., Ltd.
• Inventors: Kurokawa, Yoshiyuki, Kato, Kiyoshi
• Application Number:
  US10/128,341
• Publication Number:
  US 20020179964A1
• Time in Patent Office: Days
• US Class Current: 257/316
• CPC Class Codes: H01L 29/40114 the electrodes comprising a conductor-insulator-conductor-insulator-semiconductor structure
• CPC Class Codes: H01L 29/42324 Gate electrodes for transistors with a floating gate
• CPC Class Codes: H01L 29/7881 Programmable transistors with only two possible levels of programmation H01L29/7888 takes precedence
• CPC Class Codes: H10B 69/00 Erasable-and-programmable ROM [EPROM] devices not provided for in groups H10B41/00 - H10B63/00, e.g. ultraviolet erasable-and-programmable ROM [UVEPROM] devices

Abstract

A non-volatile memory in which a leak current from an electric charge accumulating layer to an active layer is reduced and a method of manufacturing the non-volatile memory are provided. In a non-volatile memory made from a semiconductor thin film that is formed on a substrate (101) having an insulating surface, active layer side ends (110) are tapered. This makes the thickness of a first insulating film (106), which is formed by a thermal oxidization process, at the active layer side ends (110) the same as the thickness of the rest of the first insulating film. Therefore local thinning of the first insulating film does not take place. Moreover, the tapered active layer side ends hardly tolerate electric field concentration at active layer side end corners (111). Accordingly, a leak current from an electric charge accumulating layer (107) to the active layer (105) is reduced to improve the electric charge holding characteristic. As a result, the first insulating film can be further made thin to obtain a high performance non-volatile memory that operates at a low voltage and consumes less power.

Claims

1. A non-volatile memory having a plurality of memory transistors, each of the memory transistors including:

a semiconductor having first and second impurity regions and a channel forming region;

a first insulating film that is in contact with the semiconductor;

a first gate that is in contact with the first insulating film;

a second insulating film that is in contact with the first gate; and

a second gate that is in contact with the second insulating film,

wherein, at least a region of side ends of the semiconductor that overlaps with the first insulating film and with the first gate is tapered.

2. A non-volatile memory according to claim 1, wherein the first insulating film is a thermal oxide film or a laminate that includes a thermal oxide film.

3. A non-volatile memory according to claim 1, wherein the taper angle of the tapered region is 20 to 70°

.

4. A non-volatile memory according to claim 1, wherein the tapered region is tiered to have two or more tiers, or is continuously sloped.

5. A non-volatile memory according to claim 1, wherein the memory transistors are formed on a substrate having an insulating surface.

6. A non-volatile memory according to claim 1, wherein the memory transistors are formed on an SOI substrate.

7. A non-volatile memory according to claim 1, wherein a given amount of electric charges is accumulated in the first gate of each of the memory transistors in accordance with signals inputted to the first and second impurity regions and to the second gate.

8. A method of manufacturing a non-volatile memory, comprising:

forming a tapered resist on a semiconductor;

using the tapered resist as a mask for anisotropic etching of the semiconductor to taper side ends of the semiconductor;

forming a first insulating film on the semiconductor with its side ends tapered;

forming a first gate that is in contact with the first insulating film;

forming a second insulating film that is in contact with the first gate; and

forming a second gate that is in contact with the second insulating film.

9. A method of manufacturing a non-volatile memory according to claim 8, wherein the first insulating film is a thermal oxide film or a laminate that includes a thermal oxide film.

10. A method of manufacturing a non-volatile memory according to claim 8, wherein the taper angle of the tapered region is 20 to 70°

.

11. A method of manufacturing a non-volatile memory according to claim 8, wherein the anisotropic etching of the semiconductor is multi-stage etching having two or more stages.

12. A method of manufacturing a non-volatile memory according to claim 8, wherein the selective ratio of the semiconductor and the resist is 0.2 through 2 during the anisotropic etching of the semiconductor.

14. A non-volatile memory according to claim 13, wherein said first insulating film is a thermal oxide film or a laminate that includes a thermal oxide film.

15. A non-volatile memory according to claim 13, wherein the tapered region is tiered to have two or more tiers, or is continuously sloped.

17. A non-volatile memory according to claim 16, wherein said first insulating film is a thermal oxide film or a laminate that includes a thermal oxide film.

18. A non-volatile memory according to claim 16, wherein the tapered region is tiered to have two or more tiers, or is continuously sloped.

20. A non-volatile memory according to claim 19, wherein said first insulating film is a thermal oxide film or a laminate that includes a thermal oxide film.

13. A non-volatile memory comprising:

a semiconductor film formed on an insulating surface;

a first insulating film formed on said semiconductor film;

a floating gate formed on said first insulating film;

a second insulating film formed on said floating gate; and

a control gate formed on said second insulating film,

wherein side ends of said semiconductor film are tapered.

16. A non-volatile memory comprising:

a semiconductor film comprising crystalline silicon formed on an insulating surface;

a first insulating film formed on said semiconductor film;

a floating gate formed on said first insulating film;

a second insulating film formed on said floating gate; and

a control gate formed on said second insulating film,

wherein side ends of said semiconductor film are tapered.

19. A non-volatile memory comprising:

a semiconductor film formed on an insulating surface;

a first insulating film formed on said semiconductor film;

a floating gate formed on said first insulating film;

a second insulating film formed on said floating gate; and

a control gate formed on said second insulating film,

wherein side ends of said semiconductor film are tapered at an angle of 20 to 70°

.

21. A non-volatile memory comprising:

a semiconductor film formed on an insulating surface;

a first insulating film formed on said semiconductor film;

a floating gate formed on said first insulating film;

a second insulating film formed on said floating gate; and

a control gate formed on said second insulating film,

wherein at least one side end of said semiconductor film has at least two tapered portions.

22. A non-volatile memory according to claim 21, wherein said first insulating film is a thermal oxide film or a laminate that includes a thermal oxide film.

24. A non-volatile memory according to claim 23, wherein said first insulating film is a thermal oxide film or a laminate that includes a thermal oxide film.

26. A non-volatile memory according to claim 25, wherein said first insulating film is a thermal oxide film or a laminate that includes a thermal oxide film.

23. A non-volatile memory comprising:

a semiconductor film formed on an insulating surface;

a first insulating film formed on said semiconductor film;

a floating gate formed on said first insulating film;

a second insulating film formed on said floating gate; and

a control gate formed on said second insulating film,

wherein at least one side end of said semiconductor film has at least two tapered portions.

25. A non-volatile memory comprising:

a semiconductor film formed on an insulating surface;

a first insulating film formed on said semiconductor film;

a floating gate formed on said first insulating film;

a second insulating film formed on said floating gate; and

a control gate formed on said second insulating film,

wherein at least one side end of said semiconductor film has a first tapered portion and a second tapered portion thereon,

wherein an angle of said second tapered portion is larger than that of said second tapered portion.