METHOD AND APPARATUS FOR PROCESSING SERIAL DATA USING A SINGLE RECEIVE FIFO

• US 20020188793A1
• Filed: 03/29/1999
• Published: 12/12/2002
• Est. Priority Date: 03/29/1999
• Status: Active Grant

• Current Assignee: Intel Corporation
• Original Assignee: Intel Corporation
• Inventors: HUNSAKER, MIKAL C., ABRAMSON, DARREN L., RAMAN, RAJESH, CONNELL, BRET T.
• Granted Patent: US 6,643,716 B2
• Time in Patent Office: Days
• US Class Current: 710/310
• CPC Class Codes: G06F 13/385 for adaptation of a particular data processing system to different peripheral devices
• CPC Class Codes: G06F 2213/0012 High speed serial bus, e.g. IEEE P1394

Abstract

The present invention discloses a method and apparatus for processing a packet of data received by a first-in-first-out (FIFO). In one embodiment, a message in the packet of data is recognized. Based on a plurality of control bits encoded in the message, a delimiting condition in the packet of data is determined. An operation is performed which is responsive to the delimiting condition. The operation controls the transfer of the packet of data from the FIFO to a memory.

Claims

1. A method for processing a packet of data received by a first-in-first-out (FIFO), the method comprising:

recognizing a message in the packet of data;

determining a delimiting condition in the packet of data from a plurality of control bits encoded in the message; and

performing an operation responsive to the delimiting condition, the operation controlling a transfer of the packet of data from the FIFO to a memory.

2. The method of claim 1 wherein recognizing the message includes determining if a message bit in the packet of data is asserted.

3. The method of claim 1 wherein the delimiting condition is one of a shutdown condition, an End-Of-Context (EOC) condition, a Start-Of-Packet (SOP) condition, and an End-Of-Packet (EOP) condition.

4. The method of claim 3 wherein the transfer moves data in the FIFO to a corresponding direct memory access (DMA) engine.

5. The method of claim 4 wherein, if the delimiting condition is one of a shutdown condition and an EOC condition, performing the operation further comprises:

deasserting an active bit to a FIFO decoder;

inserting an EOC message into the FIFO;

stopping accepting subsequent packets of data;

processing packets of data in the FIFO prior to the EOC message; and

shutting down the direct memory access (DMA) engine when the EOC message has been reached in the FIFO.

6. The method of claim 4 wherein, if the delimiting condition is an SOP condition, performing the operation further comprises:

obtaining SOP information in the message; and

providing the SOP information to the DMA engine.

7. The method of claim 6 wherein the SOP information includes DMA context bits and length of packet.

8. The method of claim 4 wherein, if the delimiting condition is an EOP condition, performing the operation further comprises:

obtaining EOP information in the message; and

providing the EOP information to an handler.

9. The method of claim 8 wherein the EOP information includes a speed code, an error code, and a time code.

10. The method of claim 4 wherein, if the delimiting condition is an EOP condition, performing the operation further comprises:

creating a packet trailer;

selecting the packet trailer to send to the DMA engine; and

gating a FIFO read to prevent flushing the message from the FIFO.

11. An apparatus for processing a packet of data, the apparatus comprising:

a first-in-first-out (FIFO) to store the packet of data; and

a decoder coupled to the FIFO memory, the decoder recognizing a message in the packet of data, the decoder determining a delimiting condition in the packet of data from a plurality of control bits encoded in the message and performing an operation responsive to the delimiting condition, the operation controlling a transfer of the packet of data from the FIFO to a memory.

12. The apparatus of claim 11 wherein the decoder determines if a message bit in the packet of data is asserted.

13. The apparatus of claim 11 wherein the delimiting condition is one of a shutdown condition, an End-Of-Context (EOC) condition, a Start-Of-Packet (SOP) condition, and an End-Of-Packet (EOP) condition.

14. The apparatus of claim 13 further comprises:

at least a direct memory access (DMA) engine coupled to the FIFO to transfer data from the FIFO to a bus interface unit.

15. The apparatus of claim 14 wherein, if the delimiting condition is one of a shutdown condition and an EOC condition, the operation performed by the decoder includes a deassertion of an active bit in a FIFO decoder, an insertion of an EOC message into the FIFO, a stoppage of accepting subsequent packets of data, a processing of packets of data in the FIFO prior to the EOC message, and a shutdown of the DMA engine when the EOC message has been reached in the FIFO.

16. The apparatus of claim 14 wherein, if the delimiting condition is an SOP condition, the operation performed by the decoder includes a retrieval of SOP information in the message and a transfer of the SOP information to the DMA engine.

17. The apparatus of claim 16 wherein the SOP information includes DMA context bits and length of packet.

18. The apparatus of claim 14 wherein, if the delimiting condition is an EOP condition, the operation performed by the decoder includes a retrieval of EOP information in the message and a transfer of the EOP information to an handler.

19. The apparatus of claim 18 wherein the EOP information includes a speed code, an error code, and a time code.

20. The apparatus of claim 14 further comprises:

a multiplexer coupled to the FIFO, the multiplexer selecting a packet trailer to send to the DMA engine when the delimiting condition is an EOP condition; and

a gating circuit coupled to the FIFO, the DMA engine, and a bus interface unit, the gating circuit preventing flushing the message from the FIFO by the bus interface unit.

21. A system comprising:

a first bus;

a processor coupled to the bus;

a memory coupled to the processor;

a bridge coupled to the first bus and a second bus via a physical link device, the bridge managing a transfer of a packet of data between the second bus and the processor, the bridge comprising;

a first-in-first-out (FIFO) to store the packet of data, and

a decoder coupled to the FIFO memory, the decoder recognizing a message in the packet of data, the decoder determining a delimiting condition in the packet of data from a plurality of control bits encoded in the message and performing an operation responsive to the delimiting condition, the operation controlling a transfer of the packet of data from the FIFO to the memory.

22. The system of claim 21 wherein the decoder determines if a message bit in the packet of data is asserted.

23. The system of claim 21 wherein the delimiting condition is one of a shutdown condition, an End-Of-Context (EOC) condition, a Start-Of-Packet (SOP) condition, and an End-Of-Packet (EOP) condition.

24. The system of claim 23 further comprises:

at least a direct memory access (DMA) engine coupled to the FIFO to transfer data from the FIFO to a bus interface unit.

25. The system of claim 24 wherein, if the delimiting condition is one of a shutdown condition and an EOC condition, the operation performed by the decoder includes an insertion of an EOC message into the FIFO, a deassertion of an active bit, a stoppage of accepting subsequent packets of data, a processing of packets of data in the FIFO prior to the EOC message, and a shutdown of the DMA engine when the EOC message has been reached in the FIFO.

26. The system of claim 24 wherein, if the delimiting condition is an SOP condition, the operation performed by the decoder includes a retrieval of SOP information in the message and a transfer of the SOP information to the DMA engine.

27. The system of claim 26 wherein the SOP information includes DMA context bits and length of packet.

28. The system of claim 24 wherein, if the delimiting condition is an EOP condition, the operation performed by the decoder includes a retrieval of EOP information in the message and a transfer of the EOP information to an handler.

29. The system of claim 28 wherein the EOP information includes a speed code, an error code, and a time code.

30. The system of claim 24 wherein the bridge further comprises:

a multiplexer coupled to the FIFO, the multiplexer selecting a packet trailer to send to the DMA engine when the delimiting condition is an EOP condition; and

a gating circuit coupled to the FIFO, the DMA engine, and a bus interface unit, the gating circuit preventing flushing the message from the FIFO by the bus interface unit.