Method and apparatus for processing serial data using a single receive fifo

• US 6,643,716 B2
• Filed: 03/29/1999
• Issued: 11/04/2003
• Est. Priority Date: 03/29/1999
• Status: Expired due to Fees

• Current Assignee: Intel Corporation
• Original Assignee: Intel Corporation
• Inventors: Raman, Rajesh, Connell, Bret T., Hunsaker, Mikal C., Abramson, Darren L.
• Primary Examiner(s): Gaffin, Jeffrey
• Assistant Examiner(s): Nguyen, Tanh Q.
• Application Number:
  US09/280,908
• Publication Number:
  US 20020188793A1
• Time in Patent Office: 1,681 Days
• Field of Search: 710/20, 710/21, 710/22, 710/29, 710/30, 710/33, 710/35, 710/52, 709/206, 709/207, 709/212, 709/230, 709/231, 709/236, 370/229, 370/235, 370/300, 370/349, 370/389, 370/401, 370/402, 370/412, 370/428, 370/466, 370/467, 370/470, 370/471, 370/473, 370/474, 370/476
• US Class Current: 710/21
• CPC Class Codes: G06F 13/385 for adaptation of a particular data processing system to different peripheral devices
• CPC Class Codes: G06F 2213/0012 High speed serial bus, e.g. IEEE P1394

Abstract

The present invention discloses a method and apparatus for processing a packet of data received by a first-in-first-out (FIFO). In one embodiment, a message in the packet of data is recognized. Based on a plurality of control bits encoded in the message, a delimiting condition in the packet of data is determined. An operation is performed which is responsive to the delimiting condition. The operation controls the transfer of the packet of data from the FIFO to a memory.

Claims

1. A method comprising:

determining if a quadlet in a receive packet of data is a message quadlet, the packet of data being received by a first-in-first-out (FIFO);

determining a delimiting condition in the message quadlet from a plurality of control bits encoded in the message quadlet; and

performing an operation responsive to the delimiting condition, the operation controlling a transfer of data from the receive FIFO to a memory.

2. The method of claim 1 wherein determining if the quadlet in the packet of data is a message quadlet includes determining if a message bit associated with the quadlet is asserted.

3. The method of claim 1 wherein the delimiting condition is one of an End-Of-Context (EOC) condition, a Staff-Of-Packet (SOP) condition, and an End-Of-Packet (EOP) condition.

4. The method of claim 3 wherein the transfer moves data in the FIFO to a corresponding direct memory access (DMA) engine.

5. The method of claim 4 wherein, if the delimiting condition is an EOC condition associated with the DMA engine, performing the operation comprises:

deasserting an active bit to a receive FIFO decoder;

inserting an EOC message into the FIFO; and

stopping accepting subsequent packets of data.

6. The method of claim 4 wherein, if the delimiting condition is an SOP condition, performing the operation comprises:

obtaining SOP information in the message; and

providing the SOP information to the DMA engine.

7. The method of claim 6 wherein the SOP information includes DMA context bits and length of packet.

8. The method of claim 4 wherein, if the delimiting condition is an EOP condition, performing the operation comprises:

obtaining EOP information in the message; and

providing the EOP information to an handler.

9. The method of claim 8 wherein the EOP information includes a speed code, an error code, and a time code.

10. The method of claim 4 wherein, if the delimiting condition is an EOP condition, performing the operation comprises:

creating a packet trailer;

selecting the packet trailer to send to the DMA engine; and

gating a FIFO read to prevent flushing the message from the receive FIFO.

11. An apparatus comprising:

a receive first-in-first-out (FIFO) to store a packet of data; and

a decoder and gating circuit coupled to the FIFO memory, the decoder and gating circuit determining if a quadlet in the packet of data is a message quadlet, the decoder and gating circuit determining a delimiting condition in the message quadlet from a plurality of control bits encoded in the message quadlet and performing an operation responsive to the delimiting condition, the operation controlling a transfer of data from the receive FIFO to a memory.

12. The apparatus of claim 11 wherein the decoder and gating circuit determines if a message bit associated with the quadlet is asserted.

13. The apparatus of claim 11 wherein the delimiting condition is one of an End-Of-Context (EOC) condition, a Start-Of-Packet (SOP) condition, and an End-Of-Packet (EOP) condition.

14. The apparatus of claim 13 further comprises:

at least a direct memory access (DMA) engine coupled to the receive FIFO to transfer data from the receive FIFO to a bus interface unit.

15. The apparatus of claim 14 wherein, if the delimiting condition is an EOC condition associated with the DMA engine, the operation performed by the decoder and gating circuit includes a deassertion of an active bit in a FIFO decoder, an insertion of an EOC message into the receive FIFO, and a stoppage of accepting subsequent packets of data.

16. The apparatus of claim 14 wherein, if the delimiting condition is an SOP condition, the operation performed by the decoder and gating circuit includes a retrieval of SOP information in the message and a transfer of the SOP information to the DMA engine.

17. The apparatus of claim 16 wherein the SOP information includes DMA context bits and length of packet.

18. The apparatus of claim 14 wherein, if the delimiting condition is an EOP condition, the operation performed by the decoder and gating circuit includes a retrieval of EOP information in the message and a transfer of the EOP information to an handler.

19. The apparatus of claim 18 wherein the EOP information includes a speed code, an error code, and a time code.

20. The apparatus of claim 14 further comprises:

a multiplexer coupled to the receive FIFO, the multiplexer selecting a packet trailer to send to the DMA engine when the delimiting condition is an EOP condition.

21. A system comprising:

a first bus;

a processor coupled to the bus;

a memory coupled to the processor; and

a bridge coupled to the first bus and a second bus via a physical link device, the bridge managing a transfer of a packet of data between the second bus and the processor, the bridge comprising;

a receive first-in-first-out (FIFO) to store the packet of data, and

a decoder and gating circuit coupled to the receive FIFO memory, the decoder and gating circuit determining if a quadlet in the packet of data is a message quadlet, the decoder and gating circuit determining a delimiting condition in the from a plurality of control bits encoded in the message quadlet and performing an operation responsive to the delimiting condition, the operation controlling a transfer of data from the receive FIFO to the memory.

22. The system of claim 21 wherein the decoder and gating circuit determines if a message bit associated with the quadlet is asserted.

23. The system of claim 21 wherein the delimiting condition is one of an End-Of-Context (EOC) condition, a Start-Of-Packet (SOP) condition, and an End-Of-Packet (EOP) condition.

24. The system of claim 23 further comprises:

at least a direct memory access (DMA) engine coupled to the receive FIFO to transfer data from the receive FIFO to a bus interface unit.

25. The system of claim 24 wherein, if the delimiting condition is an EOC condition associated with the DMA engine, the operation performed by the decoder and gating circuit includes an insertion of an EOC message into the receive FIFO, a deassertion of an active bit, and a stoppage of accepting subsequent packets of data.

26. The system of claim 24 wherein, if the delimiting condition is an SOP condition, the operation performed by the decoder and gating circuit includes a retrieval of SOP information in the message and a transfer of the SOP information to the DMA engine.

27. The system of claim 26 wherein the SOP information includes DMA context bits and length of packet.

28. The system of claim 24 wherein, if the delimiting condition is an EOP condition, the operation performed by the decoder and gating circuit includes a retrieval of EOP information in the message and a transfer of the EOP information to an handler.

29. The system of claim 28 wherein the EOP information includes a speed code, an error code, and a time code.

30. The system of claim 24 wherein the bridge comprises:

a multiplexer coupled to the receive FIFO, the multiplexer selecting a packet trailer to send to the DMA engine when the delimiting condition is an EOP condition.